{"id":403,"date":"2015-03-27T22:21:39","date_gmt":"2015-03-27T20:21:39","guid":{"rendered":"http:\/\/ozenozkaya.com\/blog\/?p=403"},"modified":"2015-03-27T22:21:39","modified_gmt":"2015-03-27T20:21:39","slug":"pic-programlama-3-merhaba-dunya-analizi","status":"publish","type":"post","link":"http:\/\/ozenozkaya.com\/blog\/?p=403","title":{"rendered":"PIC Programlama \u2013 3 – Merhaba D\u00fcnya Analizi"},"content":{"rendered":"

Uzunca bir d\u00f6nemdir, \u00e7ok b\u00fcy\u00fck bir yo\u011funluk i\u00e7indeyim. Bu sebepledir ki, bir t\u00fcrl\u00fc f\u0131rsat bulup yeni bir yaz\u0131ya ba\u015flayamad\u0131m. Herhalde g\u00fcn, bu g\u00fcnd\u00fcr \ud83d\ude42<\/p>\n

Geleneksel olarak yine merhaba d\u00fcnya yaz\u0131m\u0131z\u0131n suyunu s\u0131kma niyetindeyiz. Her ne kadar girizgah seviyesinde de olsa yazd\u0131\u011f\u0131m\u0131z merhaba d\u00fcnya yaz\u0131s\u0131nda, netle\u015ftirilmesi gereken baz\u0131 \u015feylerin oldu\u011fu a\u015fikar. Bu yaz\u0131 dizisinden \u00f6nce G\u00f6m\u00fcl\u00fc C yaz\u0131 dizisi<\/a>nin okunmu\u015f olmas\u0131n\u0131 \u015fiddetle tavsiye ediyorum.<\/p>\n

\u015eimdi laf\u0131 uzatmadan, PIC’de yazd\u0131\u011f\u0131m\u0131z ilk kodu hat\u0131rlayal\u0131m.<\/p>\n

#include <xc.h>\n \nvoid main(void)\n{\n TRISB=0;\n PORTB=1;\n while(1);\n}<\/pre>\n
Bir kere \u015fu xc.h’\u0131 bir inceleyelim ne varm\u0131\u015f i\u00e7inde?<\/p>\n
#ifndef _XC_H_\n#define _XC_H_\n\n#ifdef __XC8\n#include <htc.h>\n#endif\n\n#endif     \/\/_XC_H\n<\/pre>\n
G\u00f6rd\u00fc\u011f\u00fcn\u00fcz \u00fczere, XC asl\u0131nda MplabX Compiler anlam\u0131nda yer al\u0131yor ve kulland\u0131\u011f\u0131m\u0131z platform 8 bitlik oldu\u011fundan, __XC8 etiketi sistemde tan\u0131ml\u0131 oldu\u011fundan (MplabX taraf\u0131ndan, biz projeyi olu\u015fturdu\u011fumuzda otomatik tan\u0131mlan\u0131r) ilgili compiler header’\u0131 \u00e7a\u011f\u0131r\u0131lm\u0131\u015f. Bunun da “htc.h” oldu\u011funu g\u00f6r\u00fcyoruz. Burada jeton d\u00fc\u015f\u00fcyor, hmm demek ki bu xc serisi, eski hi-tech C compiler’\u0131n \u00fczerine kurulmu\u015f. Burnumuz bunun kokusunu ald\u0131. \u015eimdi daha derine inelim; htc.h’\u0131 a\u00e7al\u0131m.<\/p>\n
#ifndef _HTC_H_\n#define _HTC_H_\n\n#if defined(__CCI__) && !defined(_XC_H_)\n#warning \"CCI projects should use the top-level support file xc.hnIncluding xc.h instead\"\n#include <xc.h>\n#endif\n\n#if !defined(__CCI__) && !defined(__IAR__)\n\/* allow CCI definitions even when CCI option is not turned on *\/\n#include <cci.h>\n#endif\n\n\/* Definitions for _HTC_EDITION_ values *\/\n#define __LITE__ 0\n#define __STD__ 1\n#define __PRO__ 2\n\n\/* common definitions *\/\n\n#define    ___mkstr1(x)    #x\n#define    ___mkstr(x) ___mkstr1(x)\n\n#define _OMNITARGET    ((void *)0xFFFFFFFF)\n\nextern const char __xc8_OPTIM_SPEED;\n\n#include <xc8debug.h>\n\n\/* HI-TECH PICC \/ PICC-Lite compiler *\/\n#if    defined(__PICC__) || defined(__PICCLITE__)\n#include <pic.h>\n#endif\n\n\/* HI-TECH PICC-18 compiler *\/\n#if    defined(__PICC18__)\n#include <pic18.h>\n#endif\n\n\/* MPLAB C18 Compatibility Header *\/\n#ifdef __18CXX\n#include <pic18.h>\n#endif\n\n\/* HI-TECH dsPICC compiler *\/\n#if    defined(__DSPICC__)\n#include <dspic.h>\n#endif\n\n\/* HI-TECH C for PIC32 *\/\n#if defined(__PICC32__)\n#include <pic32.h>\n#endif\n\n#endif\n<\/pre>\n
Bu header dosyas\u0131 sayesinde, projenin \u00f6zelliklerine bak\u0131larak jenerik olarak do\u011fru header’lar\u0131n se\u00e7ilmesi sa\u011flan\u0131yor. Muhakkak ki bunlar\u0131n hepsi alt alta dallan\u0131yor ancak \u015f\u00f6yle k\u0131saca bir \u00f6zet ge\u00e7elim. CCI denilen bir muhabbet var.\u00a0The Common C Interface (CCI) kavram\u0131, ta\u015f\u0131nabilir kod yaz\u0131labilmesi i\u00e7in ortaya at\u0131lm\u0131\u015f g\u00fczel bir kavram. Ancak Microchip bence bu yar\u0131\u015fta biraz geride kalm\u0131\u015f. Yine de CCI’ya ileride de\u011finece\u011fim.<\/p>\n
xc8debug.h ise, MplabX ide \u00fczerinden yap\u0131lan debug i\u015flerine yard\u0131mc\u0131 olan, \u00e7ok \u00e7ok basit bir header. Dolay\u0131s\u0131yla \u00fczerinde \u00e7ok konu\u015fmaya de\u011fmeyecek.<\/p>\n
pic.h ise \u00f6nemli. \u00c7\u00fcnk\u00fc derleyicinin bizim i\u015flemcinin register tan\u0131mlar\u0131n\u0131 ald\u0131\u011f\u0131 k\u00fct\u00fcphane bu k\u00fct\u00fcphane. Bu i\u015f nas\u0131l oluyor? Biz projeyi yarat\u0131r iken, IDE bizim se\u00e7ti\u011fimiz i\u015flemciye g\u00f6re gidip -D ile, compiler define<\/a> yap\u0131yor. Daha sonra pic.h gibi k\u00fct\u00fcphaneler bu bilgileri kullanarak, hangi mikrodenetleyicinin\u00a0header’\u0131n\u0131n se\u00e7ilece\u011fine karar veriyor. \u00d6rne\u011fin bizim se\u00e7imimizde IDE, bizim se\u00e7ti\u011fimiz i\u015flemciye g\u00f6re -D_16F84A tan\u0131m\u0131n\u0131 yapt\u0131. Bu bilgiyi cebe at\u0131p devam edelim. pic.h’\u0131n i\u00e7ine bir bakal\u0131m.<\/p>\n
#ifndef    _PIC_H_\n#define    _PIC_H_\n\n#ifndef _HTC_H_\n#include <htc.h>\n#endif\n\n#ifdef _HAS_OSCVAL_\nextern unsigned char __osccal_val(void);\n#endif\n\n#include <pic_chip_select.h>\n\n\/* MPLAB REAL-ICE related macros & includes (currently enhanced PICs only) *\/\n#if defined(__DISABLE_REALICE_IT) || !defined(__MPLAB_REALICE__) || !defined(_PIC14E)\n    #define __TRACE(id)         \/* TRACE disabled *\/\n    #define __LOG(id,value)     \/* LOG disabled *\/\n#else\n    #if defined(__MPLAB_REALICE__)\n        #include <trace16.h>\n    #endif\n#endif\n\n#define    CLRWDT()    asm(\"clrwdt\")\n#define    SLEEP()     asm(\"sleep\")\n\/\/ function version of nop\n#pragma intrinsic(__nop)\nextern void __nop(void);\n#define NOP()      __nop()\n\n\/* _nop() has been deprecated; use __nop() *\/\n#define _nop()     __nop()\n\n#define    ASMOPT_ON()     asm(\"opt asmopt_on\")\n#define    ASMOPT_OFF()    asm(\"opt asmopt_off\")\n\n\/\/\n\/\/ Legacy Programming Macro Functions\n\/\/\n#define    __CONFIG(x) \n            __config(___mkstr(__CONFIG), ___mkstr(pic), ___mkstr(x))\n\/\/ Programs the lower 4 bits per ID location\n#define __IDLOC(w) \n            __config(___mkstr(__IDLOC), ___mkstr(pic), ___mkstr(w))\n\/\/ Variant of IDLOC for those devices that permit programming of the lower 7 bits per ID location\n#define __IDLOC7(a,b,c,d) \n            __config(___mkstr(__IDLOC7), ___mkstr(pic), a, b, c, d)\n#define    __PROG_CONFIG(a, x) \n            __config(___mkstr(__PROG_CONFIG), ___mkstr(pic), a, x)\n\n\n#if !defined(_PIC14E) && !defined(_EEADRL)\n#define _EEADRL EEADR\n#else\n#define _EEADRL EEADRL\n#endif\n#if    EEPROM_SIZE > 0\n#define __EEPROM_DATA(a, b, c, d, e, f, g, h) \n             asm(\"tpsect eeprom_data,class=EEDATA,delta=2,space=3,noexec\"); \n             asm(\"tdbt\" ___mkstr(a) \",\" ___mkstr(b) \",\" ___mkstr(c) \",\" ___mkstr(d) \",\" \n                      ___mkstr(e) \",\" ___mkstr(f) \",\" ___mkstr(g) \",\" ___mkstr(h))\n#endif\n\n\/***********************************************************************\n **** FLASH memory read\/write\/erase macros and function definitions ****\n ***********************************************************************\n * Notes:\n *  __FLASHTYPE == 0 defined in devices that can only read flash memory - cannot write eg. 16F777\n *  __FLASHTYPE == 1 defined in traditional devices that can write 1 word at a time eg. 16F877\n *  __FLASHTYPE == 2 defined in devices that can only write in 4 word blocks eg. 16F877A\n *  __FLASHTYPE == 3 defined in devices requiring 32-word block erasure before writing eg. 16F87\n *  __FLASHTYPE == undefined if device can neither read nor write program memory\n *\/\n\/\/ macro FLASH_READ returns a word stored at a flash address\n#if defined(__FLASHTYPE)\nextern unsigned int flash_read(unsigned short addr);\n#if    EEPROM_SIZE > 0\n#define FLASH_READ(addr) \n    (_EEADRL=(addr)&0xff,   \n    EEADRH=(addr)>>8, \n    WREN=0,         \n    EECON1 |= 0x80,     \n    RD=1,           \n    NOP(),          \n    NOP(),          \n    (EEDATH << 8) | EEDATA)\n#else  \/\/ FLASH_READ without EEPROM\n#define FLASH_READ(addr) \n    (_EEADRL=(addr)&0xff,   \n    EEADRH=(addr)>>8, \n    RD=1,           \n    NOP(),          \n    NOP(),          \n    (EEDATH << 8) | EEDATA)\n#endif\n#endif \/\/ end FLASH_READ\n\n\/\/ macro FLASH_WRITE used when writing only one word of data\n#if    __FLASHTYPE==2 || __FLASHTYPE==3\n\/*\n * This is not available in this version. Contact HI-TECH support for more information.\n#define FLASH_WRITE(addr,data) \n    do{ \n    unsigned short x=data;  \n    flash_copy((const unsigned short *)&x,1,addr);  \n    }while(0)\n\nextern void flash_copy(const unsigned short * source_addr,unsigned char length,unsigned short dest_addr);\n*\/\n#elif  __FLASHTYPE==1\n#define FLASH_WRITE(addr, value) \n    _EEADRL=((addr)&0xff);  \n    EEADRH=((addr)>>8);   \n    EEDATH=((value)>>8);  \n    EEDATA=((value)&0xff);  \n    EECON1 |= 0x80;     \n    WREN=1;         \n    EECON2 = 0x55;      \n    EECON2 = 0xaa;      \n    WR=1;           \n    NOP();      \n    NOP();      \n    WREN=0\n\/\/extern void flash_copy(const unsigned short * source_addr,unsigned char length,unsigned short dest_addr);\n#endif \/\/ end FLASH_WRITE\n\n\/\/ macro FLASH_ERASE used to clear a 32-Byte sector of flash\n#if    __FLASHTYPE==3\n#define FLASH_ERASE(addr) \n        while(WR)continue; \n    _EEADRL=((addr)&0xFF); \n    EEADRH=((addr>>8)&0xFF); \n    EECON1=0x94; \n    CARRY=0;if(GIE)CARRY=1;GIE=0;\n    EECON2=0x55;EECON2=0xAA;WR=1; \n    NOP(); \n    if(CARRY)GIE=1 \n\n    \/\/ library function version\nextern void flash_erase(unsigned short addr);\n#endif \/\/ end FLASH_ERASE\n\n#include <eeprom_routines.h>\n\n#ifdef __PICCPRO__\n\/****************************************************************\/\n\/* Built-in delay routine                   *\/\n\/****************************************************************\/\n#pragma intrinsic(_delay)\nextern __nonreentrant void _delay(unsigned long);\n\/\/ NOTE: To use the macros below, YOU must have previously defined _XTAL_FREQ\n#define __delay_us(x) _delay((unsigned long)((x)*(_XTAL_FREQ\/4000000.0)))\n#define __delay_ms(x) _delay((unsigned long)((x)*(_XTAL_FREQ\/4000.0)))\n#endif\n\n\/****************************************************************\/\n\/****** Global interrupt enable\/disable macro definitions *******\/\n\/****************************************************************\/\n#if defined(_PIC14) || defined(_PIC14E)\n    \n#ifndef    ei\n#define    ei()    (GIE = 1)   \/\/ interrupt enable bit\n#endif  \n\n#if defined(_14000) ||  defined(_16C61) || defined(_16C62) ||\n    defined(_16C63) || defined(_16C63A) || defined(_16C64) ||\n    defined(_16C65) || defined(_16C65B) || defined(_16C71) ||\n    defined(_16C73) || defined(_16C73B) || defined(_16C74) ||\n    defined(_16C74B) || defined(_16C84) || defined(_16C745) ||\n    defined(_16C765) || defined(_16LC74B)\n    #ifndef di\n        #define di()    { do { GIE = 0; } while ( GIE == 1 ); } \/\/ disable interrupt bit\n    #endif  \n#else\n    #ifndef di\n        #define di()    (GIE = 0)   \/\/ interrupt enable bit\n    #endif  \n#endif\n\n#endif\n\n\/* The below reflect the state of TO and PD, respectively, which would otherwise\n   be trashed by startup code. *\/\nextern unsigned char __resetbits;\nextern __bit __powerdown;\nextern __bit __timeout;\n#endif \/* _PIC_H *\/\n<\/pre>\n
Arkada\u015flar sa\u011folsunlar pic.h i\u00e7inde bize yard\u0131mc\u0131 olabilecek \u00e7ok say\u0131da \u015fey tan\u0131mlam\u0131\u015flar.\u00a0pic_chip_select.h tam olarak mikrokontrol\u00f6r header’\u0131 se\u00e7imini yap\u0131yor ve onu mutlaka konu\u015faca\u011f\u0131z. Ancak s\u0131rayla buradaki baz\u0131 ibretlere bir de\u011finelim. PIC16F84A; 68 byte RAM’i ve 1024 word’l\u00fck inan\u0131lmaz(!) FLASH belle\u011fi ile, hakikaten k\u0131s\u0131tl\u0131 kaynakl\u0131 bir donan\u0131m oldu\u011fundan, day\u0131lar hakl\u0131 olarak LOG ve TRACE fonksiyonelitelerini kapatm\u0131\u015flar \ud83d\ude42 Zira bu fonksiyoneliteleri kullanmaya kalksayd\u0131k, kaynaklar\u0131n \u00e7o\u011funu kullanm\u0131\u015f olurduk.<\/p>\n
#define    CLRWDT()    asm(\"clrwdt\")\n#define    SLEEP()     asm(\"sleep\")<\/pre>\n
Yukar\u0131daki etiketler, assembler komutlar\u0131n\u0131 \u00e7a\u011f\u0131rarak s\u0131ras\u0131yla watchdog timer’\u0131 resetlemenin ve uyku moduna girmenin verimli implementasyonlar\u0131 olarak g\u00f6ze \u00e7arp\u0131yor. Watchdog timer’\u0131 resetlemek baz\u0131 arkada\u015flara bir anlam ifade etmemi\u015f olabilir. Mikrodenetleyici bir sebepten donarsa filan, reset atabilecek bir donan\u0131m\u0131n olmas\u0131 gerekiyor. E\u011fer mikrodenetleyicideki kod, belli aral\u0131klarla watchdog timer’\u0131n sayac\u0131n\u0131 s\u0131f\u0131rlamazsa, saya\u00e7 art\u0131p ta\u015far ve ta\u015ft\u0131\u011f\u0131 gibi mikrodenetleyiciye reset atar. Yerli yerinde kullan\u0131ld\u0131\u011f\u0131nda WDT (watchdog timer) cand\u0131r \ud83d\ude42 Sleep ise, mikrodenetleyiciyi d\u00fc\u015f\u00fck g\u00fc\u00e7 t\u00fcketimi moduna sokman\u0131n g\u00fczel bir yoludur. Bu k\u0131sm\u0131 da ileride detayl\u0131ca ele alaca\u011f\u0131z.<\/p>\n
ei(); ve di(); fonksiyonlar\u0131 ile s\u0131rasyla interrupt enable ve interrupt disable i\u015fleri kolayla\u015ft\u0131r\u0131lm\u0131\u015f. \u0130leride detayl\u0131ca de\u011finece\u011fimiz kesme fonksiyonelitesinin aktive edilmesi ya da devre d\u0131\u015f\u0131 b\u0131rak\u0131lmas\u0131 i\u00e7in bu makrolar\u0131 kullanmak m\u00fcmk\u00fcn \ud83d\ude42 Di\u011fer k\u0131s\u0131mlar zaten benzer. \u00d6yleyse \u015fimdi\u00a0pic_chip_select.h k\u00fct\u00fcphanesinin bir k\u0131sm\u0131n\u0131 inceleyelim. Gerisi de zaten ayn\u0131 \ud83d\ude00<\/p>\n
...\n\n#ifdef _16F84\n#ifdef _LEGACY_HEADERS\n#include <pic1684_legacy.h>\n#undef _HEADER_NOT_FOUND\n#else\n#include <pic16f84.h>\n#undef _HEADER_NOT_FOUND\n#endif\n#endif\n\n#ifdef _16F84A\n#ifdef _LEGACY_HEADERS\n#include <pic1684_legacy.h>\n#undef _HEADER_NOT_FOUND\n#else\n#include <pic16f84a.h>\n#undef _HEADER_NOT_FOUND\n#endif\n#endif\n\n...<\/pre>\n
Bu dosyada g\u00f6rd\u00fc\u011f\u00fcn\u00fcz gibi, IDE taraf\u0131ndan biz projeyi olu\u015ftururken tan\u0131mlanan etiketler kullan\u0131larak do\u011fru ba\u015fl\u0131k dosyalar\u0131 (header files) projeye dahil ediliyor yani \u00e7a\u011f\u0131r\u0131l\u0131yor. Bu saydede biz xc.h dedi\u011fimizde, mikrokontrol\u00f6r modeline g\u00f6re, ba\u015fl\u0131k dosyalar\u0131 otomatik \u00e7a\u011f\u0131r\u0131lm\u0131\u015f oluyor. Hmm, g\u00fczel \ud83d\ude42 \u00d6yleyse bir ad\u0131m daha dalal\u0131m.<\/p>\n
\/\/ Version 1.34\n\/\/ Generated 16\/02\/2015 GMT\n\n\/*\n * Copyright \u00c2\u00a9 2015, Microchip Technology Inc. and its subsidiaries (\"Microchip\")\n * All rights reserved.\n * \n * This software is developed by Microchip Technology Inc. and its subsidiaries (\"Microchip\").\n * \n * Redistribution and use in source and binary forms, with or without modification, are\n * permitted provided that the following conditions are met:\n * \n *     1. Redistributions of source code must retain the above copyright notice, this list of\n *        conditions and the following disclaimer.\n * \n *     2. Redistributions in binary form must reproduce the above copyright notice, this list\n *        of conditions and the following disclaimer in the documentation and\/or other\n *        materials provided with the distribution.\n * \n *     3. Microchip's name may not be used to endorse or promote products derived from this\n *        software without specific prior written permission.\n * \n * THIS SOFTWARE IS PROVIDED BY MICROCHIP \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES,\n * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO\n * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\n * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *  *\/\n\n#ifndef _PIC16F84A_H_\n#define _PIC16F84A_H_\n\n\/*\n * C Header file for the Microchip PIC Microcontroller\n * PIC16F84A\n *  *\/\n#ifndef __XC8\n#warning Header file pic16f84a.h included directly. Use #include <xc.h> instead.\n#endif\n\n\/*\n * Register Definitions\n *  *\/\n\n\/\/ Register: INDF\nextern volatile unsigned char           INDF                @ 0x000;\n#ifndef _LIB_BUILD\nasm(\"INDF equ 00h\");\n#endif\n\n\/\/ Register: TMR0\nextern volatile unsigned char           TMR0                @ 0x001;\n#ifndef _LIB_BUILD\nasm(\"TMR0 equ 01h\");\n#endif\n\n\/\/ Register: PCL\nextern volatile unsigned char           PCL                 @ 0x002;\n#ifndef _LIB_BUILD\nasm(\"PCL equ 02h\");\n#endif\n\n\/\/ Register: STATUS\nextern volatile unsigned char           STATUS              @ 0x003;\n#ifndef _LIB_BUILD\nasm(\"STATUS equ 03h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned C                      :1;\n        unsigned DC                     :1;\n        unsigned Z                      :1;\n        unsigned nPD                    :1;\n        unsigned nTO                    :1;\n        unsigned RP                     :2;\n        unsigned IRP                    :1;\n    };\n    struct {\n        unsigned                        :5;\n        unsigned RP0                    :1;\n        unsigned RP1                    :1;\n    };\n    struct {\n        unsigned CARRY                  :1;\n    };\n    struct {\n        unsigned                        :2;\n        unsigned ZERO                   :1;\n    };\n} STATUSbits_t;\nextern volatile STATUSbits_t STATUSbits @ 0x003;\n\/\/ bitfield macros\n#define _STATUS_C_POSN                                      0x0\n#define _STATUS_C_POSITION                                  0x0\n#define _STATUS_C_SIZE                                      0x1\n#define _STATUS_C_LENGTH                                    0x1\n#define _STATUS_C_MASK                                      0x1\n#define _STATUS_DC_POSN                                     0x1\n#define _STATUS_DC_POSITION                                 0x1\n#define _STATUS_DC_SIZE                                     0x1\n#define _STATUS_DC_LENGTH                                   0x1\n#define _STATUS_DC_MASK                                     0x2\n#define _STATUS_Z_POSN                                      0x2\n#define _STATUS_Z_POSITION                                  0x2\n#define _STATUS_Z_SIZE                                      0x1\n#define _STATUS_Z_LENGTH                                    0x1\n#define _STATUS_Z_MASK                                      0x4\n#define _STATUS_nPD_POSN                                    0x3\n#define _STATUS_nPD_POSITION                                0x3\n#define _STATUS_nPD_SIZE                                    0x1\n#define _STATUS_nPD_LENGTH                                  0x1\n#define _STATUS_nPD_MASK                                    0x8\n#define _STATUS_nTO_POSN                                    0x4\n#define _STATUS_nTO_POSITION                                0x4\n#define _STATUS_nTO_SIZE                                    0x1\n#define _STATUS_nTO_LENGTH                                  0x1\n#define _STATUS_nTO_MASK                                    0x10\n#define _STATUS_RP_POSN                                     0x5\n#define _STATUS_RP_POSITION                                 0x5\n#define _STATUS_RP_SIZE                                     0x2\n#define _STATUS_RP_LENGTH                                   0x2\n#define _STATUS_RP_MASK                                     0x60\n#define _STATUS_IRP_POSN                                    0x7\n#define _STATUS_IRP_POSITION                                0x7\n#define _STATUS_IRP_SIZE                                    0x1\n#define _STATUS_IRP_LENGTH                                  0x1\n#define _STATUS_IRP_MASK                                    0x80\n#define _STATUS_RP0_POSN                                    0x5\n#define _STATUS_RP0_POSITION                                0x5\n#define _STATUS_RP0_SIZE                                    0x1\n#define _STATUS_RP0_LENGTH                                  0x1\n#define _STATUS_RP0_MASK                                    0x20\n#define _STATUS_RP1_POSN                                    0x6\n#define _STATUS_RP1_POSITION                                0x6\n#define _STATUS_RP1_SIZE                                    0x1\n#define _STATUS_RP1_LENGTH                                  0x1\n#define _STATUS_RP1_MASK                                    0x40\n#define _STATUS_CARRY_POSN                                  0x0\n#define _STATUS_CARRY_POSITION                              0x0\n#define _STATUS_CARRY_SIZE                                  0x1\n#define _STATUS_CARRY_LENGTH                                0x1\n#define _STATUS_CARRY_MASK                                  0x1\n#define _STATUS_ZERO_POSN                                   0x2\n#define _STATUS_ZERO_POSITION                               0x2\n#define _STATUS_ZERO_SIZE                                   0x1\n#define _STATUS_ZERO_LENGTH                                 0x1\n#define _STATUS_ZERO_MASK                                   0x4\n\n\/\/ Register: FSR\nextern volatile unsigned char           FSR                 @ 0x004;\n#ifndef _LIB_BUILD\nasm(\"FSR equ 04h\");\n#endif\n\n\/\/ Register: PORTA\nextern volatile unsigned char           PORTA               @ 0x005;\n#ifndef _LIB_BUILD\nasm(\"PORTA equ 05h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned RA0                    :1;\n        unsigned RA1                    :1;\n        unsigned RA2                    :1;\n        unsigned RA3                    :1;\n        unsigned RA4                    :1;\n    };\n} PORTAbits_t;\nextern volatile PORTAbits_t PORTAbits @ 0x005;\n\/\/ bitfield macros\n#define _PORTA_RA0_POSN                                     0x0\n#define _PORTA_RA0_POSITION                                 0x0\n#define _PORTA_RA0_SIZE                                     0x1\n#define _PORTA_RA0_LENGTH                                   0x1\n#define _PORTA_RA0_MASK                                     0x1\n#define _PORTA_RA1_POSN                                     0x1\n#define _PORTA_RA1_POSITION                                 0x1\n#define _PORTA_RA1_SIZE                                     0x1\n#define _PORTA_RA1_LENGTH                                   0x1\n#define _PORTA_RA1_MASK                                     0x2\n#define _PORTA_RA2_POSN                                     0x2\n#define _PORTA_RA2_POSITION                                 0x2\n#define _PORTA_RA2_SIZE                                     0x1\n#define _PORTA_RA2_LENGTH                                   0x1\n#define _PORTA_RA2_MASK                                     0x4\n#define _PORTA_RA3_POSN                                     0x3\n#define _PORTA_RA3_POSITION                                 0x3\n#define _PORTA_RA3_SIZE                                     0x1\n#define _PORTA_RA3_LENGTH                                   0x1\n#define _PORTA_RA3_MASK                                     0x8\n#define _PORTA_RA4_POSN                                     0x4\n#define _PORTA_RA4_POSITION                                 0x4\n#define _PORTA_RA4_SIZE                                     0x1\n#define _PORTA_RA4_LENGTH                                   0x1\n#define _PORTA_RA4_MASK                                     0x10\n\n\/\/ Register: PORTB\nextern volatile unsigned char           PORTB               @ 0x006;\n#ifndef _LIB_BUILD\nasm(\"PORTB equ 06h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned RB0                    :1;\n        unsigned RB1                    :1;\n        unsigned RB2                    :1;\n        unsigned RB3                    :1;\n        unsigned RB4                    :1;\n        unsigned RB5                    :1;\n        unsigned RB6                    :1;\n        unsigned RB7                    :1;\n    };\n} PORTBbits_t;\nextern volatile PORTBbits_t PORTBbits @ 0x006;\n\/\/ bitfield macros\n#define _PORTB_RB0_POSN                                     0x0\n#define _PORTB_RB0_POSITION                                 0x0\n#define _PORTB_RB0_SIZE                                     0x1\n#define _PORTB_RB0_LENGTH                                   0x1\n#define _PORTB_RB0_MASK                                     0x1\n#define _PORTB_RB1_POSN                                     0x1\n#define _PORTB_RB1_POSITION                                 0x1\n#define _PORTB_RB1_SIZE                                     0x1\n#define _PORTB_RB1_LENGTH                                   0x1\n#define _PORTB_RB1_MASK                                     0x2\n#define _PORTB_RB2_POSN                                     0x2\n#define _PORTB_RB2_POSITION                                 0x2\n#define _PORTB_RB2_SIZE                                     0x1\n#define _PORTB_RB2_LENGTH                                   0x1\n#define _PORTB_RB2_MASK                                     0x4\n#define _PORTB_RB3_POSN                                     0x3\n#define _PORTB_RB3_POSITION                                 0x3\n#define _PORTB_RB3_SIZE                                     0x1\n#define _PORTB_RB3_LENGTH                                   0x1\n#define _PORTB_RB3_MASK                                     0x8\n#define _PORTB_RB4_POSN                                     0x4\n#define _PORTB_RB4_POSITION                                 0x4\n#define _PORTB_RB4_SIZE                                     0x1\n#define _PORTB_RB4_LENGTH                                   0x1\n#define _PORTB_RB4_MASK                                     0x10\n#define _PORTB_RB5_POSN                                     0x5\n#define _PORTB_RB5_POSITION                                 0x5\n#define _PORTB_RB5_SIZE                                     0x1\n#define _PORTB_RB5_LENGTH                                   0x1\n#define _PORTB_RB5_MASK                                     0x20\n#define _PORTB_RB6_POSN                                     0x6\n#define _PORTB_RB6_POSITION                                 0x6\n#define _PORTB_RB6_SIZE                                     0x1\n#define _PORTB_RB6_LENGTH                                   0x1\n#define _PORTB_RB6_MASK                                     0x40\n#define _PORTB_RB7_POSN                                     0x7\n#define _PORTB_RB7_POSITION                                 0x7\n#define _PORTB_RB7_SIZE                                     0x1\n#define _PORTB_RB7_LENGTH                                   0x1\n#define _PORTB_RB7_MASK                                     0x80\n\n\/\/ Register: EEDATA\nextern volatile unsigned char           EEDATA              @ 0x008;\n#ifndef _LIB_BUILD\nasm(\"EEDATA equ 08h\");\n#endif\n\n\/\/ Register: EEADR\nextern volatile unsigned char           EEADR               @ 0x009;\n#ifndef _LIB_BUILD\nasm(\"EEADR equ 09h\");\n#endif\n\n\/\/ Register: PCLATH\nextern volatile unsigned char           PCLATH              @ 0x00A;\n#ifndef _LIB_BUILD\nasm(\"PCLATH equ 0Ah\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned PCLATH                 :5;\n    };\n} PCLATHbits_t;\nextern volatile PCLATHbits_t PCLATHbits @ 0x00A;\n\/\/ bitfield macros\n#define _PCLATH_PCLATH_POSN                                 0x0\n#define _PCLATH_PCLATH_POSITION                             0x0\n#define _PCLATH_PCLATH_SIZE                                 0x5\n#define _PCLATH_PCLATH_LENGTH                               0x5\n#define _PCLATH_PCLATH_MASK                                 0x1F\n\n\/\/ Register: INTCON\nextern volatile unsigned char           INTCON              @ 0x00B;\n#ifndef _LIB_BUILD\nasm(\"INTCON equ 0Bh\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned RBIF                   :1;\n        unsigned INTF                   :1;\n        unsigned T0IF                   :1;\n        unsigned RBIE                   :1;\n        unsigned INTE                   :1;\n        unsigned T0IE                   :1;\n        unsigned EEIE                   :1;\n        unsigned GIE                    :1;\n    };\n    struct {\n        unsigned                        :2;\n        unsigned TMR0IF                 :1;\n        unsigned                        :2;\n        unsigned TMR0IE                 :1;\n    };\n} INTCONbits_t;\nextern volatile INTCONbits_t INTCONbits @ 0x00B;\n\/\/ bitfield macros\n#define _INTCON_RBIF_POSN                                   0x0\n#define _INTCON_RBIF_POSITION                               0x0\n#define _INTCON_RBIF_SIZE                                   0x1\n#define _INTCON_RBIF_LENGTH                                 0x1\n#define _INTCON_RBIF_MASK                                   0x1\n#define _INTCON_INTF_POSN                                   0x1\n#define _INTCON_INTF_POSITION                               0x1\n#define _INTCON_INTF_SIZE                                   0x1\n#define _INTCON_INTF_LENGTH                                 0x1\n#define _INTCON_INTF_MASK                                   0x2\n#define _INTCON_T0IF_POSN                                   0x2\n#define _INTCON_T0IF_POSITION                               0x2\n#define _INTCON_T0IF_SIZE                                   0x1\n#define _INTCON_T0IF_LENGTH                                 0x1\n#define _INTCON_T0IF_MASK                                   0x4\n#define _INTCON_RBIE_POSN                                   0x3\n#define _INTCON_RBIE_POSITION                               0x3\n#define _INTCON_RBIE_SIZE                                   0x1\n#define _INTCON_RBIE_LENGTH                                 0x1\n#define _INTCON_RBIE_MASK                                   0x8\n#define _INTCON_INTE_POSN                                   0x4\n#define _INTCON_INTE_POSITION                               0x4\n#define _INTCON_INTE_SIZE                                   0x1\n#define _INTCON_INTE_LENGTH                                 0x1\n#define _INTCON_INTE_MASK                                   0x10\n#define _INTCON_T0IE_POSN                                   0x5\n#define _INTCON_T0IE_POSITION                               0x5\n#define _INTCON_T0IE_SIZE                                   0x1\n#define _INTCON_T0IE_LENGTH                                 0x1\n#define _INTCON_T0IE_MASK                                   0x20\n#define _INTCON_EEIE_POSN                                   0x6\n#define _INTCON_EEIE_POSITION                               0x6\n#define _INTCON_EEIE_SIZE                                   0x1\n#define _INTCON_EEIE_LENGTH                                 0x1\n#define _INTCON_EEIE_MASK                                   0x40\n#define _INTCON_GIE_POSN                                    0x7\n#define _INTCON_GIE_POSITION                                0x7\n#define _INTCON_GIE_SIZE                                    0x1\n#define _INTCON_GIE_LENGTH                                  0x1\n#define _INTCON_GIE_MASK                                    0x80\n#define _INTCON_TMR0IF_POSN                                 0x2\n#define _INTCON_TMR0IF_POSITION                             0x2\n#define _INTCON_TMR0IF_SIZE                                 0x1\n#define _INTCON_TMR0IF_LENGTH                               0x1\n#define _INTCON_TMR0IF_MASK                                 0x4\n#define _INTCON_TMR0IE_POSN                                 0x5\n#define _INTCON_TMR0IE_POSITION                             0x5\n#define _INTCON_TMR0IE_SIZE                                 0x1\n#define _INTCON_TMR0IE_LENGTH                               0x1\n#define _INTCON_TMR0IE_MASK                                 0x20\n\n\/\/ Register: OPTION_REG\nextern volatile unsigned char           OPTION_REG          @ 0x081;\n#ifndef _LIB_BUILD\nasm(\"OPTION_REG equ 081h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned PS                     :3;\n        unsigned PSA                    :1;\n        unsigned T0SE                   :1;\n        unsigned T0CS                   :1;\n        unsigned INTEDG                 :1;\n        unsigned nRBPU                  :1;\n    };\n    struct {\n        unsigned PS0                    :1;\n        unsigned PS1                    :1;\n        unsigned PS2                    :1;\n    };\n} OPTION_REGbits_t;\nextern volatile OPTION_REGbits_t OPTION_REGbits @ 0x081;\n\/\/ bitfield macros\n#define _OPTION_REG_PS_POSN                                 0x0\n#define _OPTION_REG_PS_POSITION                             0x0\n#define _OPTION_REG_PS_SIZE                                 0x3\n#define _OPTION_REG_PS_LENGTH                               0x3\n#define _OPTION_REG_PS_MASK                                 0x7\n#define _OPTION_REG_PSA_POSN                                0x3\n#define _OPTION_REG_PSA_POSITION                            0x3\n#define _OPTION_REG_PSA_SIZE                                0x1\n#define _OPTION_REG_PSA_LENGTH                              0x1\n#define _OPTION_REG_PSA_MASK                                0x8\n#define _OPTION_REG_T0SE_POSN                               0x4\n#define _OPTION_REG_T0SE_POSITION                           0x4\n#define _OPTION_REG_T0SE_SIZE                               0x1\n#define _OPTION_REG_T0SE_LENGTH                             0x1\n#define _OPTION_REG_T0SE_MASK                               0x10\n#define _OPTION_REG_T0CS_POSN                               0x5\n#define _OPTION_REG_T0CS_POSITION                           0x5\n#define _OPTION_REG_T0CS_SIZE                               0x1\n#define _OPTION_REG_T0CS_LENGTH                             0x1\n#define _OPTION_REG_T0CS_MASK                               0x20\n#define _OPTION_REG_INTEDG_POSN                             0x6\n#define _OPTION_REG_INTEDG_POSITION                         0x6\n#define _OPTION_REG_INTEDG_SIZE                             0x1\n#define _OPTION_REG_INTEDG_LENGTH                           0x1\n#define _OPTION_REG_INTEDG_MASK                             0x40\n#define _OPTION_REG_nRBPU_POSN                              0x7\n#define _OPTION_REG_nRBPU_POSITION                          0x7\n#define _OPTION_REG_nRBPU_SIZE                              0x1\n#define _OPTION_REG_nRBPU_LENGTH                            0x1\n#define _OPTION_REG_nRBPU_MASK                              0x80\n#define _OPTION_REG_PS0_POSN                                0x0\n#define _OPTION_REG_PS0_POSITION                            0x0\n#define _OPTION_REG_PS0_SIZE                                0x1\n#define _OPTION_REG_PS0_LENGTH                              0x1\n#define _OPTION_REG_PS0_MASK                                0x1\n#define _OPTION_REG_PS1_POSN                                0x1\n#define _OPTION_REG_PS1_POSITION                            0x1\n#define _OPTION_REG_PS1_SIZE                                0x1\n#define _OPTION_REG_PS1_LENGTH                              0x1\n#define _OPTION_REG_PS1_MASK                                0x2\n#define _OPTION_REG_PS2_POSN                                0x2\n#define _OPTION_REG_PS2_POSITION                            0x2\n#define _OPTION_REG_PS2_SIZE                                0x1\n#define _OPTION_REG_PS2_LENGTH                              0x1\n#define _OPTION_REG_PS2_MASK                                0x4\n\n\/\/ Register: TRISA\nextern volatile unsigned char           TRISA               @ 0x085;\n#ifndef _LIB_BUILD\nasm(\"TRISA equ 085h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned TRISA0                 :1;\n        unsigned TRISA1                 :1;\n        unsigned TRISA2                 :1;\n        unsigned TRISA3                 :1;\n        unsigned TRISA4                 :1;\n    };\n} TRISAbits_t;\nextern volatile TRISAbits_t TRISAbits @ 0x085;\n\/\/ bitfield macros\n#define _TRISA_TRISA0_POSN                                  0x0\n#define _TRISA_TRISA0_POSITION                              0x0\n#define _TRISA_TRISA0_SIZE                                  0x1\n#define _TRISA_TRISA0_LENGTH                                0x1\n#define _TRISA_TRISA0_MASK                                  0x1\n#define _TRISA_TRISA1_POSN                                  0x1\n#define _TRISA_TRISA1_POSITION                              0x1\n#define _TRISA_TRISA1_SIZE                                  0x1\n#define _TRISA_TRISA1_LENGTH                                0x1\n#define _TRISA_TRISA1_MASK                                  0x2\n#define _TRISA_TRISA2_POSN                                  0x2\n#define _TRISA_TRISA2_POSITION                              0x2\n#define _TRISA_TRISA2_SIZE                                  0x1\n#define _TRISA_TRISA2_LENGTH                                0x1\n#define _TRISA_TRISA2_MASK                                  0x4\n#define _TRISA_TRISA3_POSN                                  0x3\n#define _TRISA_TRISA3_POSITION                              0x3\n#define _TRISA_TRISA3_SIZE                                  0x1\n#define _TRISA_TRISA3_LENGTH                                0x1\n#define _TRISA_TRISA3_MASK                                  0x8\n#define _TRISA_TRISA4_POSN                                  0x4\n#define _TRISA_TRISA4_POSITION                              0x4\n#define _TRISA_TRISA4_SIZE                                  0x1\n#define _TRISA_TRISA4_LENGTH                                0x1\n#define _TRISA_TRISA4_MASK                                  0x10\n\n\/\/ Register: TRISB\nextern volatile unsigned char           TRISB               @ 0x086;\n#ifndef _LIB_BUILD\nasm(\"TRISB equ 086h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned TRISB0                 :1;\n        unsigned TRISB1                 :1;\n        unsigned TRISB2                 :1;\n        unsigned TRISB3                 :1;\n        unsigned TRISB4                 :1;\n        unsigned TRISB5                 :1;\n        unsigned TRISB6                 :1;\n        unsigned TRISB7                 :1;\n    };\n} TRISBbits_t;\nextern volatile TRISBbits_t TRISBbits @ 0x086;\n\/\/ bitfield macros\n#define _TRISB_TRISB0_POSN                                  0x0\n#define _TRISB_TRISB0_POSITION                              0x0\n#define _TRISB_TRISB0_SIZE                                  0x1\n#define _TRISB_TRISB0_LENGTH                                0x1\n#define _TRISB_TRISB0_MASK                                  0x1\n#define _TRISB_TRISB1_POSN                                  0x1\n#define _TRISB_TRISB1_POSITION                              0x1\n#define _TRISB_TRISB1_SIZE                                  0x1\n#define _TRISB_TRISB1_LENGTH                                0x1\n#define _TRISB_TRISB1_MASK                                  0x2\n#define _TRISB_TRISB2_POSN                                  0x2\n#define _TRISB_TRISB2_POSITION                              0x2\n#define _TRISB_TRISB2_SIZE                                  0x1\n#define _TRISB_TRISB2_LENGTH                                0x1\n#define _TRISB_TRISB2_MASK                                  0x4\n#define _TRISB_TRISB3_POSN                                  0x3\n#define _TRISB_TRISB3_POSITION                              0x3\n#define _TRISB_TRISB3_SIZE                                  0x1\n#define _TRISB_TRISB3_LENGTH                                0x1\n#define _TRISB_TRISB3_MASK                                  0x8\n#define _TRISB_TRISB4_POSN                                  0x4\n#define _TRISB_TRISB4_POSITION                              0x4\n#define _TRISB_TRISB4_SIZE                                  0x1\n#define _TRISB_TRISB4_LENGTH                                0x1\n#define _TRISB_TRISB4_MASK                                  0x10\n#define _TRISB_TRISB5_POSN                                  0x5\n#define _TRISB_TRISB5_POSITION                              0x5\n#define _TRISB_TRISB5_SIZE                                  0x1\n#define _TRISB_TRISB5_LENGTH                                0x1\n#define _TRISB_TRISB5_MASK                                  0x20\n#define _TRISB_TRISB6_POSN                                  0x6\n#define _TRISB_TRISB6_POSITION                              0x6\n#define _TRISB_TRISB6_SIZE                                  0x1\n#define _TRISB_TRISB6_LENGTH                                0x1\n#define _TRISB_TRISB6_MASK                                  0x40\n#define _TRISB_TRISB7_POSN                                  0x7\n#define _TRISB_TRISB7_POSITION                              0x7\n#define _TRISB_TRISB7_SIZE                                  0x1\n#define _TRISB_TRISB7_LENGTH                                0x1\n#define _TRISB_TRISB7_MASK                                  0x80\n\n\/\/ Register: EECON1\nextern volatile unsigned char           EECON1              @ 0x088;\n#ifndef _LIB_BUILD\nasm(\"EECON1 equ 088h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned RD                     :1;\n        unsigned WR                     :1;\n        unsigned WREN                   :1;\n        unsigned WRERR                  :1;\n        unsigned EEIF                   :1;\n    };\n} EECON1bits_t;\nextern volatile EECON1bits_t EECON1bits @ 0x088;\n\/\/ bitfield macros\n#define _EECON1_RD_POSN                                     0x0\n#define _EECON1_RD_POSITION                                 0x0\n#define _EECON1_RD_SIZE                                     0x1\n#define _EECON1_RD_LENGTH                                   0x1\n#define _EECON1_RD_MASK                                     0x1\n#define _EECON1_WR_POSN                                     0x1\n#define _EECON1_WR_POSITION                                 0x1\n#define _EECON1_WR_SIZE                                     0x1\n#define _EECON1_WR_LENGTH                                   0x1\n#define _EECON1_WR_MASK                                     0x2\n#define _EECON1_WREN_POSN                                   0x2\n#define _EECON1_WREN_POSITION                               0x2\n#define _EECON1_WREN_SIZE                                   0x1\n#define _EECON1_WREN_LENGTH                                 0x1\n#define _EECON1_WREN_MASK                                   0x4\n#define _EECON1_WRERR_POSN                                  0x3\n#define _EECON1_WRERR_POSITION                              0x3\n#define _EECON1_WRERR_SIZE                                  0x1\n#define _EECON1_WRERR_LENGTH                                0x1\n#define _EECON1_WRERR_MASK                                  0x8\n#define _EECON1_EEIF_POSN                                   0x4\n#define _EECON1_EEIF_POSITION                               0x4\n#define _EECON1_EEIF_SIZE                                   0x1\n#define _EECON1_EEIF_LENGTH                                 0x1\n#define _EECON1_EEIF_MASK                                   0x10\n\n\/\/ Register: EECON2\nextern volatile unsigned char           EECON2              @ 0x089;\n#ifndef _LIB_BUILD\nasm(\"EECON2 equ 089h\");\n#endif\n\n\/*\n * Bit Definitions\n *  *\/\n#define _DEPRECATED __attribute__((__deprecated__))\n#ifndef BANKMASK\n#define BANKMASK(addr) ((addr)&07Fh)\n#endif\nextern volatile __bit                   CARRY               @ (((unsigned) &STATUS)*8) + 0;\n#define                                 CARRY_bit           BANKMASK(STATUS), 0\nextern volatile __bit                   DC                  @ (((unsigned) &STATUS)*8) + 1;\n#define                                 DC_bit              BANKMASK(STATUS), 1\nextern volatile __bit                   EEIE                @ (((unsigned) &INTCON)*8) + 6;\n#define                                 EEIE_bit            BANKMASK(INTCON), 6\nextern volatile __bit                   EEIF                @ (((unsigned) &EECON1)*8) + 4;\n#define                                 EEIF_bit            BANKMASK(EECON1), 4\nextern volatile __bit                   GIE                 @ (((unsigned) &INTCON)*8) + 7;\n#define                                 GIE_bit             BANKMASK(INTCON), 7\nextern volatile __bit                   INTE                @ (((unsigned) &INTCON)*8) + 4;\n#define                                 INTE_bit            BANKMASK(INTCON), 4\nextern volatile __bit                   INTEDG              @ (((unsigned) &OPTION_REG)*8) + 6;\n#define                                 INTEDG_bit          BANKMASK(OPTION_REG), 6\nextern volatile __bit                   INTF                @ (((unsigned) &INTCON)*8) + 1;\n#define                                 INTF_bit            BANKMASK(INTCON), 1\nextern volatile __bit                   IRP                 @ (((unsigned) &STATUS)*8) + 7;\n#define                                 IRP_bit             BANKMASK(STATUS), 7\nextern volatile __bit                   PS0                 @ (((unsigned) &OPTION_REG)*8) + 0;\n#define                                 PS0_bit             BANKMASK(OPTION_REG), 0\nextern volatile __bit                   PS1                 @ (((unsigned) &OPTION_REG)*8) + 1;\n#define                                 PS1_bit             BANKMASK(OPTION_REG), 1\nextern volatile __bit                   PS2                 @ (((unsigned) &OPTION_REG)*8) + 2;\n#define                                 PS2_bit             BANKMASK(OPTION_REG), 2\nextern volatile __bit                   PSA                 @ (((unsigned) &OPTION_REG)*8) + 3;\n#define                                 PSA_bit             BANKMASK(OPTION_REG), 3\nextern volatile __bit                   RA0                 @ (((unsigned) &PORTA)*8) + 0;\n#define                                 RA0_bit             BANKMASK(PORTA), 0\nextern volatile __bit                   RA1                 @ (((unsigned) &PORTA)*8) + 1;\n#define                                 RA1_bit             BANKMASK(PORTA), 1\nextern volatile __bit                   RA2                 @ (((unsigned) &PORTA)*8) + 2;\n#define                                 RA2_bit             BANKMASK(PORTA), 2\nextern volatile __bit                   RA3                 @ (((unsigned) &PORTA)*8) + 3;\n#define                                 RA3_bit             BANKMASK(PORTA), 3\nextern volatile __bit                   RA4                 @ (((unsigned) &PORTA)*8) + 4;\n#define                                 RA4_bit             BANKMASK(PORTA), 4\nextern volatile __bit                   RB0                 @ (((unsigned) &PORTB)*8) + 0;\n#define                                 RB0_bit             BANKMASK(PORTB), 0\nextern volatile __bit                   RB1                 @ (((unsigned) &PORTB)*8) + 1;\n#define                                 RB1_bit             BANKMASK(PORTB), 1\nextern volatile __bit                   RB2                 @ (((unsigned) &PORTB)*8) + 2;\n#define                                 RB2_bit             BANKMASK(PORTB), 2\nextern volatile __bit                   RB3                 @ (((unsigned) &PORTB)*8) + 3;\n#define                                 RB3_bit             BANKMASK(PORTB), 3\nextern volatile __bit                   RB4                 @ (((unsigned) &PORTB)*8) + 4;\n#define                                 RB4_bit             BANKMASK(PORTB), 4\nextern volatile __bit                   RB5                 @ (((unsigned) &PORTB)*8) + 5;\n#define                                 RB5_bit             BANKMASK(PORTB), 5\nextern volatile __bit                   RB6                 @ (((unsigned) &PORTB)*8) + 6;\n#define                                 RB6_bit             BANKMASK(PORTB), 6\nextern volatile __bit                   RB7                 @ (((unsigned) &PORTB)*8) + 7;\n#define                                 RB7_bit             BANKMASK(PORTB), 7\nextern volatile __bit                   RBIE                @ (((unsigned) &INTCON)*8) + 3;\n#define                                 RBIE_bit            BANKMASK(INTCON), 3\nextern volatile __bit                   RBIF                @ (((unsigned) &INTCON)*8) + 0;\n#define                                 RBIF_bit            BANKMASK(INTCON), 0\nextern volatile __bit                   RD                  @ (((unsigned) &EECON1)*8) + 0;\n#define                                 RD_bit              BANKMASK(EECON1), 0\nextern volatile __bit                   RP0                 @ (((unsigned) &STATUS)*8) + 5;\n#define                                 RP0_bit             BANKMASK(STATUS), 5\nextern volatile __bit                   RP1                 @ (((unsigned) &STATUS)*8) + 6;\n#define                                 RP1_bit             BANKMASK(STATUS), 6\nextern volatile __bit                   T0CS                @ (((unsigned) &OPTION_REG)*8) + 5;\n#define                                 T0CS_bit            BANKMASK(OPTION_REG), 5\nextern volatile __bit                   T0IE                @ (((unsigned) &INTCON)*8) + 5;\n#define                                 T0IE_bit            BANKMASK(INTCON), 5\nextern volatile __bit                   T0IF                @ (((unsigned) &INTCON)*8) + 2;\n#define                                 T0IF_bit            BANKMASK(INTCON), 2\nextern volatile __bit                   T0SE                @ (((unsigned) &OPTION_REG)*8) + 4;\n#define                                 T0SE_bit            BANKMASK(OPTION_REG), 4\nextern volatile __bit                   TMR0IE              @ (((unsigned) &INTCON)*8) + 5;\n#define                                 TMR0IE_bit          BANKMASK(INTCON), 5\nextern volatile __bit                   TMR0IF              @ (((unsigned) &INTCON)*8) + 2;\n#define                                 TMR0IF_bit          BANKMASK(INTCON), 2\nextern volatile __bit                   TRISA0              @ (((unsigned) &TRISA)*8) + 0;\n#define                                 TRISA0_bit          BANKMASK(TRISA), 0\nextern volatile __bit                   TRISA1              @ (((unsigned) &TRISA)*8) + 1;\n#define                                 TRISA1_bit          BANKMASK(TRISA), 1\nextern volatile __bit                   TRISA2              @ (((unsigned) &TRISA)*8) + 2;\n#define                                 TRISA2_bit          BANKMASK(TRISA), 2\nextern volatile __bit                   TRISA3              @ (((unsigned) &TRISA)*8) + 3;\n#define                                 TRISA3_bit          BANKMASK(TRISA), 3\nextern volatile __bit                   TRISA4              @ (((unsigned) &TRISA)*8) + 4;\n#define                                 TRISA4_bit          BANKMASK(TRISA), 4\nextern volatile __bit                   TRISB0              @ (((unsigned) &TRISB)*8) + 0;\n#define                                 TRISB0_bit          BANKMASK(TRISB), 0\nextern volatile __bit                   TRISB1              @ (((unsigned) &TRISB)*8) + 1;\n#define                                 TRISB1_bit          BANKMASK(TRISB), 1\nextern volatile __bit                   TRISB2              @ (((unsigned) &TRISB)*8) + 2;\n#define                                 TRISB2_bit          BANKMASK(TRISB), 2\nextern volatile __bit                   TRISB3              @ (((unsigned) &TRISB)*8) + 3;\n#define                                 TRISB3_bit          BANKMASK(TRISB), 3\nextern volatile __bit                   TRISB4              @ (((unsigned) &TRISB)*8) + 4;\n#define                                 TRISB4_bit          BANKMASK(TRISB), 4\nextern volatile __bit                   TRISB5              @ (((unsigned) &TRISB)*8) + 5;\n#define                                 TRISB5_bit          BANKMASK(TRISB), 5\nextern volatile __bit                   TRISB6              @ (((unsigned) &TRISB)*8) + 6;\n#define                                 TRISB6_bit          BANKMASK(TRISB), 6\nextern volatile __bit                   TRISB7              @ (((unsigned) &TRISB)*8) + 7;\n#define                                 TRISB7_bit          BANKMASK(TRISB), 7\nextern volatile __bit                   WR                  @ (((unsigned) &EECON1)*8) + 1;\n#define                                 WR_bit              BANKMASK(EECON1), 1\nextern volatile __bit                   WREN                @ (((unsigned) &EECON1)*8) + 2;\n#define                                 WREN_bit            BANKMASK(EECON1), 2\nextern volatile __bit                   WRERR               @ (((unsigned) &EECON1)*8) + 3;\n#define                                 WRERR_bit           BANKMASK(EECON1), 3\nextern volatile __bit                   ZERO                @ (((unsigned) &STATUS)*8) + 2;\n#define                                 ZERO_bit            BANKMASK(STATUS), 2\nextern volatile __bit                   nPD                 @ (((unsigned) &STATUS)*8) + 3;\n#define                                 nPD_bit             BANKMASK(STATUS), 3\nextern volatile __bit                   nRBPU               @ (((unsigned) &OPTION_REG)*8) + 7;\n#define                                 nRBPU_bit           BANKMASK(OPTION_REG), 7\nextern volatile __bit                   nTO                 @ (((unsigned) &STATUS)*8) + 4;\n#define                                 nTO_bit             BANKMASK(STATUS), 4\n\n#endif \/\/ _PIC16F84A_H_\n<\/pre>\n
Burada, t\u00fcm register tan\u0131mlar\u0131n\u0131n nas\u0131l yap\u0131ld\u0131\u011f\u0131na dikkat ediniz \ud83d\ude42 Bizim G\u00f6m\u00fcl\u00fc C yaz\u0131 dizisini tamamen okuyan herkes i\u00e7in burada ne yap\u0131ld\u0131\u011f\u0131n\u0131 anlamak kolay olacakt\u0131r. Yine de anlamad\u0131\u011f\u0131n\u0131z yerler olursa sorunuz \ud83d\ude42 \u015eimdi merhaba d\u00fcnya kodumuzdaki register’lar\u0131 \u00f6zellikle inceleyelim.<\/p>\n
...\n\/\/ Register: PORTB\nextern volatile unsigned char           PORTB               @ 0x006;\n#ifndef _LIB_BUILD\nasm(\"PORTB equ 06h\");\n#endif\n\n...\n\/\/ Register: TRISB\nextern volatile unsigned char           TRISB               @ 0x086;\n#ifndef _LIB_BUILD\nasm(\"TRISB equ 086h\");\n#endif<\/pre>\n
Burada demi\u015fler ki PORTB diye bir de\u011fi\u015fken yarat\u0131yoruz ve bu bellekteki 0x006 numaral\u0131 adrese kar\u015f\u0131l\u0131k d\u00fc\u015f\u00fcyor. Yine benzer \u015fekilde\u00a0TRISB diye bir de\u011fi\u015fken yarat\u0131yoruz ve bu bellekteki 0x086 numaral\u0131 adrese kar\u015f\u0131l\u0131k d\u00fc\u015f\u00fcyor. Bu bilgileri datasheet’teki <\/a>bellek haritas\u0131ndan aynen do\u011frulamak m\u00fcmk\u00fcn. Zaten oradan bak\u0131p yazm\u0131\u015flar \ud83d\ude42 Ama ay\u0131betmi\u015fler… \u00c7\u00fcnk\u00fc t\u00fcm register’lar i\u00e7in kafadan de\u011fi\u015fken tan\u0131mlanm\u0131\u015f. Bu, \u00f6demesi a\u011f\u0131r bir bedel. Ayr\u0131ca @ operat\u00f6r\u00fc standart bir operat\u00f6r de\u011fil. Dolay\u0131s\u0131yla bu tan\u0131mlar, platform ba\u011f\u0131ml\u0131l\u0131\u011f\u0131 yaratmakta ve kodlar\u0131n ta\u015f\u0131nabilirli\u011fini negatif etkilemekte. Bunlara bir ayar \u00e7ekmemiz ka\u00e7\u0131n\u0131lmaz duruyor \ud83d\ude42<\/p>\n
\u015eimdi, bu noktaya geldikten sonra, gelene\u011fimizi uygulayal\u0131m ve yine header kullanmaks\u0131z\u0131n merhaba d\u00fcnya kodumuzu yeniden yazal\u0131m \ud83d\ude42<\/p>\n
#define myTRISB (*( volatile unsigned char*)0x086)\n#define myPORTB (*( volatile unsigned char*)0x006)\n\nvoid main() {\n    myTRISB = 0;\n    myPORTB = 1;\n    while(1);\n}\n<\/pre>\n
G\u00f6rd\u00fc\u011f\u00fcn\u00fcz \u00fczere, kodda ne bir k\u00fct\u00fcphane kulland\u0131k, ne de bir de\u011fi\u015fken! Zaten kodumuzda, merhaba d\u00fcnya kodundaki gereksiz \u015feylerin hi\u00e7 birisi yok. Register\u00a0tan\u0131mlar\u0131n\u0131 da \u00e7ok \u00e7ok daha verimli \u015fekilde yapt\u0131\u011f\u0131m\u0131z\u0131 gururla huzurlar\u0131n\u0131za sunar\u0131m \ud83d\ude42 0 byte de\u011fi\u015fken kullanarak, yine ledimizi yakt\u0131k!<\/p>\n
\"PIC16F84A_3\"<\/a><\/p>\n
Buradan gerekli ibretleri l\u00fctfen alal\u0131m \ud83d\ude42 San\u0131yorum ki, “Abi PIC programlama yaparken Hi-Tech compiler CSS’den iyiymi\u015f yaa” filan gibi geyiklere art\u0131k bolca g\u00fclersiniz. Hi\u00e7birine ihtiyac\u0131m\u0131z yok, sadece tekerle\u011fi yeniden icad etmemek i\u00e7in onlar\u0131 ara\u00e7 olarak kullan\u0131yoruz \ud83d\ude09<\/p>\n
Sonraki yaz\u0131mda bu temellerin \u00fczerine, giri\u015f \u00e7\u0131k\u0131\u015f i\u015flemleriyle ilgili detayl\u0131 bir yap\u0131 in\u015fa etmeyi planl\u0131yorum. Dilerim sizler i\u00e7in de faydal\u0131 ve e\u011flenceli bir yaz\u0131 olmu\u015ftur.<\/p>\n
\u015eimdi devam…<\/p>\n<\/i> \u00d6nceki Sayfa<\/span><\/a> \u00a0<\/i> Sonraki Sayfa<\/span><\/a>\n
 <\/p>\n","protected":false},"excerpt":{"rendered":"
Uzunca bir d\u00f6nemdir, \u00e7ok b\u00fcy\u00fck bir yo\u011funluk i\u00e7indeyim. Bu sebepledir ki, bir t\u00fcrl\u00fc f\u0131rsat bulup yeni bir yaz\u0131ya ba\u015flayamad\u0131m. Herhalde g\u00fcn, bu g\u00fcnd\u00fcr \ud83d\ude42 Geleneksel olarak yine merhaba d\u00fcnya yaz\u0131m\u0131z\u0131n suyunu s\u0131kma niyetindeyiz. Her ne kadar girizgah seviyesinde de olsa yazd\u0131\u011f\u0131m\u0131z merhaba d\u00fcnya yaz\u0131s\u0131nda, netle\u015ftirilmesi gereken baz\u0131 \u015feylerin oldu\u011fu a\u015fikar. Bu yaz\u0131 dizisinden \u00f6nce G\u00f6m\u00fcl\u00fc Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_tr_post_content":"Uzunca bir d\u00f6nemdir, \u00e7ok b\u00fcy\u00fck bir yo\u011funluk i\u00e7indeyim. Bu sebepledir ki, bir t\u00fcrl\u00fc f\u0131rsat bulup yeni bir yaz\u0131ya ba\u015flayamad\u0131m. Herhalde g\u00fcn, bu g\u00fcnd\u00fcr :)\n\nGeleneksel olarak yine merhaba d\u00fcnya yaz\u0131m\u0131z\u0131n suyunu s\u0131kma niyetindeyiz. Her ne kadar girizgah seviyesinde de olsa yazd\u0131\u011f\u0131m\u0131z merhaba d\u00fcnya yaz\u0131s\u0131nda, netle\u015ftirilmesi gereken baz\u0131 \u015feylerin oldu\u011fu a\u015fikar. Bu yaz\u0131 dizisinden \u00f6nce G\u00f6m\u00fcl\u00fc C yaz\u0131 dizisi<\/a>nin okunmu\u015f olmas\u0131n\u0131 \u015fiddetle tavsiye ediyorum.\n\n\u015eimdi laf\u0131 uzatmadan, PIC'de yazd\u0131\u011f\u0131m\u0131z ilk kodu hat\u0131rlayal\u0131m.\n\n
#include <xc.h>\n \nvoid main(void)\n{\n TRISB=0;\n PORTB=1;\n while(1);\n}<\/pre>\n\nBir kere \u015fu xc.h'\u0131 bir inceleyelim ne varm\u0131\u015f i\u00e7inde?\n\n
#ifndef _XC_H_\n#define _XC_H_\n\n#ifdef __XC8\n#include <htc.h>\n#endif\n\n#endif     \/\/_XC_H\n<\/pre>\n\nG\u00f6rd\u00fc\u011f\u00fcn\u00fcz \u00fczere, XC asl\u0131nda MplabX Compiler anlam\u0131nda yer al\u0131yor ve kulland\u0131\u011f\u0131m\u0131z platform 8 bitlik oldu\u011fundan, __XC8 etiketi sistemde tan\u0131ml\u0131 oldu\u011fundan (MplabX taraf\u0131ndan, biz projeyi olu\u015fturdu\u011fumuzda otomatik tan\u0131mlan\u0131r) ilgili compiler header'\u0131 \u00e7a\u011f\u0131r\u0131lm\u0131\u015f. Bunun da \"htc.h\" oldu\u011funu g\u00f6r\u00fcyoruz. Burada jeton d\u00fc\u015f\u00fcyor, hmm demek ki bu xc serisi, eski hi-tech C compiler'\u0131n \u00fczerine kurulmu\u015f. Burnumuz bunun kokusunu ald\u0131. \u015eimdi daha derine inelim; htc.h'\u0131 a\u00e7al\u0131m.\n\n
#ifndef _HTC_H_\n#define _HTC_H_\n\n#if defined(__CCI__) && !defined(_XC_H_)\n#warning \"CCI projects should use the top-level support file xc.hnIncluding xc.h instead\"\n#include <xc.h>\n#endif\n\n#if !defined(__CCI__) && !defined(__IAR__)\n\/* allow CCI definitions even when CCI option is not turned on *\/\n#include <cci.h>\n#endif\n\n\/* Definitions for _HTC_EDITION_ values *\/\n#define __LITE__ 0\n#define __STD__ 1\n#define __PRO__ 2\n\n\/* common definitions *\/\n\n#define    ___mkstr1(x)    #x\n#define    ___mkstr(x) ___mkstr1(x)\n\n#define _OMNITARGET    ((void *)0xFFFFFFFF)\n\nextern const char __xc8_OPTIM_SPEED;\n\n#include <xc8debug.h>\n\n\/* HI-TECH PICC \/ PICC-Lite compiler *\/\n#if    defined(__PICC__) || defined(__PICCLITE__)\n#include <pic.h>\n#endif\n\n\/* HI-TECH PICC-18 compiler *\/\n#if    defined(__PICC18__)\n#include <pic18.h>\n#endif\n\n\/* MPLAB C18 Compatibility Header *\/\n#ifdef __18CXX\n#include <pic18.h>\n#endif\n\n\/* HI-TECH dsPICC compiler *\/\n#if    defined(__DSPICC__)\n#include <dspic.h>\n#endif\n\n\/* HI-TECH C for PIC32 *\/\n#if defined(__PICC32__)\n#include <pic32.h>\n#endif\n\n#endif\n<\/pre>\n\nBu header dosyas\u0131 sayesinde, projenin \u00f6zelliklerine bak\u0131larak jenerik olarak do\u011fru header'lar\u0131n se\u00e7ilmesi sa\u011flan\u0131yor. Muhakkak ki bunlar\u0131n hepsi alt alta dallan\u0131yor ancak \u015f\u00f6yle k\u0131saca bir \u00f6zet ge\u00e7elim. CCI denilen bir muhabbet var.\u00a0The Common C Interface (CCI) kavram\u0131, ta\u015f\u0131nabilir kod yaz\u0131labilmesi i\u00e7in ortaya at\u0131lm\u0131\u015f g\u00fczel bir kavram. Ancak Microchip bence bu yar\u0131\u015fta biraz geride kalm\u0131\u015f. Yine de CCI'ya ileride de\u011finece\u011fim.\n\nxc8debug.h ise, MplabX ide \u00fczerinden yap\u0131lan debug i\u015flerine yard\u0131mc\u0131 olan, \u00e7ok \u00e7ok basit bir header. Dolay\u0131s\u0131yla \u00fczerinde \u00e7ok konu\u015fmaya de\u011fmeyecek.\n\npic.h ise \u00f6nemli. \u00c7\u00fcnk\u00fc derleyicinin bizim i\u015flemcinin register tan\u0131mlar\u0131n\u0131 ald\u0131\u011f\u0131 k\u00fct\u00fcphane bu k\u00fct\u00fcphane. Bu i\u015f nas\u0131l oluyor? Biz projeyi yarat\u0131r iken, IDE bizim se\u00e7ti\u011fimiz i\u015flemciye g\u00f6re gidip -D ile, compiler define<\/a> yap\u0131yor. Daha sonra pic.h gibi k\u00fct\u00fcphaneler bu bilgileri kullanarak, hangi mikrodenetleyicinin\u00a0header'\u0131n\u0131n se\u00e7ilece\u011fine karar veriyor. \u00d6rne\u011fin bizim se\u00e7imimizde IDE, bizim se\u00e7ti\u011fimiz i\u015flemciye g\u00f6re -D_16F84A tan\u0131m\u0131n\u0131 yapt\u0131. Bu bilgiyi cebe at\u0131p devam edelim. pic.h'\u0131n i\u00e7ine bir bakal\u0131m.\n\n
#ifndef    _PIC_H_\n#define    _PIC_H_\n\n#ifndef _HTC_H_\n#include <htc.h>\n#endif\n\n#ifdef _HAS_OSCVAL_\nextern unsigned char __osccal_val(void);\n#endif\n\n#include <pic_chip_select.h>\n\n\/* MPLAB REAL-ICE related macros & includes (currently enhanced PICs only) *\/\n#if defined(__DISABLE_REALICE_IT) || !defined(__MPLAB_REALICE__) || !defined(_PIC14E)\n    #define __TRACE(id)         \/* TRACE disabled *\/\n    #define __LOG(id,value)     \/* LOG disabled *\/\n#else\n    #if defined(__MPLAB_REALICE__)\n        #include <trace16.h>\n    #endif\n#endif\n\n#define    CLRWDT()    asm(\"clrwdt\")\n#define    SLEEP()     asm(\"sleep\")\n\/\/ function version of nop\n#pragma intrinsic(__nop)\nextern void __nop(void);\n#define NOP()      __nop()\n\n\/* _nop() has been deprecated; use __nop() *\/\n#define _nop()     __nop()\n\n#define    ASMOPT_ON()     asm(\"opt asmopt_on\")\n#define    ASMOPT_OFF()    asm(\"opt asmopt_off\")\n\n\/\/\n\/\/ Legacy Programming Macro Functions\n\/\/\n#define    __CONFIG(x) \n            __config(___mkstr(__CONFIG), ___mkstr(pic), ___mkstr(x))\n\/\/ Programs the lower 4 bits per ID location\n#define __IDLOC(w) \n            __config(___mkstr(__IDLOC), ___mkstr(pic), ___mkstr(w))\n\/\/ Variant of IDLOC for those devices that permit programming of the lower 7 bits per ID location\n#define __IDLOC7(a,b,c,d) \n            __config(___mkstr(__IDLOC7), ___mkstr(pic), a, b, c, d)\n#define    __PROG_CONFIG(a, x) \n            __config(___mkstr(__PROG_CONFIG), ___mkstr(pic), a, x)\n\n\n#if !defined(_PIC14E) && !defined(_EEADRL)\n#define _EEADRL EEADR\n#else\n#define _EEADRL EEADRL\n#endif\n#if    EEPROM_SIZE > 0\n#define __EEPROM_DATA(a, b, c, d, e, f, g, h) \n             asm(\"tpsect eeprom_data,class=EEDATA,delta=2,space=3,noexec\"); \n             asm(\"tdbt\" ___mkstr(a) \",\" ___mkstr(b) \",\" ___mkstr(c) \",\" ___mkstr(d) \",\" \n                      ___mkstr(e) \",\" ___mkstr(f) \",\" ___mkstr(g) \",\" ___mkstr(h))\n#endif\n\n\/***********************************************************************\n **** FLASH memory read\/write\/erase macros and function definitions ****\n ***********************************************************************\n * Notes:\n *  __FLASHTYPE == 0 defined in devices that can only read flash memory - cannot write eg. 16F777\n *  __FLASHTYPE == 1 defined in traditional devices that can write 1 word at a time eg. 16F877\n *  __FLASHTYPE == 2 defined in devices that can only write in 4 word blocks eg. 16F877A\n *  __FLASHTYPE == 3 defined in devices requiring 32-word block erasure before writing eg. 16F87\n *  __FLASHTYPE == undefined if device can neither read nor write program memory\n *\/\n\/\/ macro FLASH_READ returns a word stored at a flash address\n#if defined(__FLASHTYPE)\nextern unsigned int flash_read(unsigned short addr);\n#if    EEPROM_SIZE > 0\n#define FLASH_READ(addr) \n    (_EEADRL=(addr)&0xff,   \n    EEADRH=(addr)>>8, \n    WREN=0,         \n    EECON1 |= 0x80,     \n    RD=1,           \n    NOP(),          \n    NOP(),          \n    (EEDATH << 8) | EEDATA)\n#else  \/\/ FLASH_READ without EEPROM\n#define FLASH_READ(addr) \n    (_EEADRL=(addr)&0xff,   \n    EEADRH=(addr)>>8, \n    RD=1,           \n    NOP(),          \n    NOP(),          \n    (EEDATH << 8) | EEDATA)\n#endif\n#endif \/\/ end FLASH_READ\n\n\/\/ macro FLASH_WRITE used when writing only one word of data\n#if    __FLASHTYPE==2 || __FLASHTYPE==3\n\/*\n * This is not available in this version. Contact HI-TECH support for more information.\n#define FLASH_WRITE(addr,data) \n    do{ \n    unsigned short x=data;  \n    flash_copy((const unsigned short *)&x,1,addr);  \n    }while(0)\n\nextern void flash_copy(const unsigned short * source_addr,unsigned char length,unsigned short dest_addr);\n*\/\n#elif  __FLASHTYPE==1\n#define FLASH_WRITE(addr, value) \n    _EEADRL=((addr)&0xff);  \n    EEADRH=((addr)>>8);   \n    EEDATH=((value)>>8);  \n    EEDATA=((value)&0xff);  \n    EECON1 |= 0x80;     \n    WREN=1;         \n    EECON2 = 0x55;      \n    EECON2 = 0xaa;      \n    WR=1;           \n    NOP();      \n    NOP();      \n    WREN=0\n\/\/extern void flash_copy(const unsigned short * source_addr,unsigned char length,unsigned short dest_addr);\n#endif \/\/ end FLASH_WRITE\n\n\/\/ macro FLASH_ERASE used to clear a 32-Byte sector of flash\n#if    __FLASHTYPE==3\n#define FLASH_ERASE(addr) \n        while(WR)continue; \n    _EEADRL=((addr)&0xFF); \n    EEADRH=((addr>>8)&0xFF); \n    EECON1=0x94; \n    CARRY=0;if(GIE)CARRY=1;GIE=0;\n    EECON2=0x55;EECON2=0xAA;WR=1; \n    NOP(); \n    if(CARRY)GIE=1 \n\n    \/\/ library function version\nextern void flash_erase(unsigned short addr);\n#endif \/\/ end FLASH_ERASE\n\n#include <eeprom_routines.h>\n\n#ifdef __PICCPRO__\n\/****************************************************************\/\n\/* Built-in delay routine                   *\/\n\/****************************************************************\/\n#pragma intrinsic(_delay)\nextern __nonreentrant void _delay(unsigned long);\n\/\/ NOTE: To use the macros below, YOU must have previously defined _XTAL_FREQ\n#define __delay_us(x) _delay((unsigned long)((x)*(_XTAL_FREQ\/4000000.0)))\n#define __delay_ms(x) _delay((unsigned long)((x)*(_XTAL_FREQ\/4000.0)))\n#endif\n\n\/****************************************************************\/\n\/****** Global interrupt enable\/disable macro definitions *******\/\n\/****************************************************************\/\n#if defined(_PIC14) || defined(_PIC14E)\n    \n#ifndef    ei\n#define    ei()    (GIE = 1)   \/\/ interrupt enable bit\n#endif  \n\n#if defined(_14000) ||  defined(_16C61) || defined(_16C62) ||\n    defined(_16C63) || defined(_16C63A) || defined(_16C64) ||\n    defined(_16C65) || defined(_16C65B) || defined(_16C71) ||\n    defined(_16C73) || defined(_16C73B) || defined(_16C74) ||\n    defined(_16C74B) || defined(_16C84) || defined(_16C745) ||\n    defined(_16C765) || defined(_16LC74B)\n    #ifndef di\n        #define di()    { do { GIE = 0; } while ( GIE == 1 ); } \/\/ disable interrupt bit\n    #endif  \n#else\n    #ifndef di\n        #define di()    (GIE = 0)   \/\/ interrupt enable bit\n    #endif  \n#endif\n\n#endif\n\n\/* The below reflect the state of TO and PD, respectively, which would otherwise\n   be trashed by startup code. *\/\nextern unsigned char __resetbits;\nextern __bit __powerdown;\nextern __bit __timeout;\n#endif \/* _PIC_H *\/\n<\/pre>\n\nArkada\u015flar sa\u011folsunlar pic.h i\u00e7inde bize yard\u0131mc\u0131 olabilecek \u00e7ok say\u0131da \u015fey tan\u0131mlam\u0131\u015flar.\u00a0pic_chip_select.h tam olarak mikrokontrol\u00f6r header'\u0131 se\u00e7imini yap\u0131yor ve onu mutlaka konu\u015faca\u011f\u0131z. Ancak s\u0131rayla buradaki baz\u0131 ibretlere bir de\u011finelim. PIC16F84A; 68 byte RAM'i ve 1024 word'l\u00fck inan\u0131lmaz(!) FLASH belle\u011fi ile, hakikaten k\u0131s\u0131tl\u0131 kaynakl\u0131 bir donan\u0131m oldu\u011fundan, day\u0131lar hakl\u0131 olarak LOG ve TRACE fonksiyonelitelerini kapatm\u0131\u015flar :) Zira bu fonksiyoneliteleri kullanmaya kalksayd\u0131k, kaynaklar\u0131n \u00e7o\u011funu kullanm\u0131\u015f olurduk.\n\n
#define    CLRWDT()    asm(\"clrwdt\")\n#define    SLEEP()     asm(\"sleep\")<\/pre>\n\nYukar\u0131daki etiketler, assembler komutlar\u0131n\u0131 \u00e7a\u011f\u0131rarak s\u0131ras\u0131yla watchdog timer'\u0131 resetlemenin ve uyku moduna girmenin verimli implementasyonlar\u0131 olarak g\u00f6ze \u00e7arp\u0131yor. Watchdog timer'\u0131 resetlemek baz\u0131 arkada\u015flara bir anlam ifade etmemi\u015f olabilir. Mikrodenetleyici bir sebepten donarsa filan, reset atabilecek bir donan\u0131m\u0131n olmas\u0131 gerekiyor. E\u011fer mikrodenetleyicideki kod, belli aral\u0131klarla watchdog timer'\u0131n sayac\u0131n\u0131 s\u0131f\u0131rlamazsa, saya\u00e7 art\u0131p ta\u015far ve ta\u015ft\u0131\u011f\u0131 gibi mikrodenetleyiciye reset atar. Yerli yerinde kullan\u0131ld\u0131\u011f\u0131nda WDT (watchdog timer) cand\u0131r :) Sleep ise, mikrodenetleyiciyi d\u00fc\u015f\u00fck g\u00fc\u00e7 t\u00fcketimi moduna sokman\u0131n g\u00fczel bir yoludur. Bu k\u0131sm\u0131 da ileride detayl\u0131ca ele alaca\u011f\u0131z.\n\nei(); ve di(); fonksiyonlar\u0131 ile s\u0131rasyla interrupt enable ve interrupt disable i\u015fleri kolayla\u015ft\u0131r\u0131lm\u0131\u015f. \u0130leride detayl\u0131ca de\u011finece\u011fimiz kesme fonksiyonelitesinin aktive edilmesi ya da devre d\u0131\u015f\u0131 b\u0131rak\u0131lmas\u0131 i\u00e7in bu makrolar\u0131 kullanmak m\u00fcmk\u00fcn :) Di\u011fer k\u0131s\u0131mlar zaten benzer. \u00d6yleyse \u015fimdi\u00a0pic_chip_select.h k\u00fct\u00fcphanesinin bir k\u0131sm\u0131n\u0131 inceleyelim. Gerisi de zaten ayn\u0131 :D\n\n
...\n\n#ifdef _16F84\n#ifdef _LEGACY_HEADERS\n#include <pic1684_legacy.h>\n#undef _HEADER_NOT_FOUND\n#else\n#include <pic16f84.h>\n#undef _HEADER_NOT_FOUND\n#endif\n#endif\n\n#ifdef _16F84A\n#ifdef _LEGACY_HEADERS\n#include <pic1684_legacy.h>\n#undef _HEADER_NOT_FOUND\n#else\n#include <pic16f84a.h>\n#undef _HEADER_NOT_FOUND\n#endif\n#endif\n\n...<\/pre>\n\nBu dosyada g\u00f6rd\u00fc\u011f\u00fcn\u00fcz gibi, IDE taraf\u0131ndan biz projeyi olu\u015ftururken tan\u0131mlanan etiketler kullan\u0131larak do\u011fru ba\u015fl\u0131k dosyalar\u0131 (header files) projeye dahil ediliyor yani \u00e7a\u011f\u0131r\u0131l\u0131yor. Bu saydede biz xc.h dedi\u011fimizde, mikrokontrol\u00f6r modeline g\u00f6re, ba\u015fl\u0131k dosyalar\u0131 otomatik \u00e7a\u011f\u0131r\u0131lm\u0131\u015f oluyor. Hmm, g\u00fczel :) \u00d6yleyse bir ad\u0131m daha dalal\u0131m.\n\n
\/\/ Version 1.34\n\/\/ Generated 16\/02\/2015 GMT\n\n\/*\n * Copyright \u00c2\u00a9 2015, Microchip Technology Inc. and its subsidiaries (\"Microchip\")\n * All rights reserved.\n * \n * This software is developed by Microchip Technology Inc. and its subsidiaries (\"Microchip\").\n * \n * Redistribution and use in source and binary forms, with or without modification, are\n * permitted provided that the following conditions are met:\n * \n *     1. Redistributions of source code must retain the above copyright notice, this list of\n *        conditions and the following disclaimer.\n * \n *     2. Redistributions in binary form must reproduce the above copyright notice, this list\n *        of conditions and the following disclaimer in the documentation and\/or other\n *        materials provided with the distribution.\n * \n *     3. Microchip's name may not be used to endorse or promote products derived from this\n *        software without specific prior written permission.\n * \n * THIS SOFTWARE IS PROVIDED BY MICROCHIP \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES,\n * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO\n * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\n * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *  *\/\n\n#ifndef _PIC16F84A_H_\n#define _PIC16F84A_H_\n\n\/*\n * C Header file for the Microchip PIC Microcontroller\n * PIC16F84A\n *  *\/\n#ifndef __XC8\n#warning Header file pic16f84a.h included directly. Use #include <xc.h> instead.\n#endif\n\n\/*\n * Register Definitions\n *  *\/\n\n\/\/ Register: INDF\nextern volatile unsigned char           INDF                @ 0x000;\n#ifndef _LIB_BUILD\nasm(\"INDF equ 00h\");\n#endif\n\n\/\/ Register: TMR0\nextern volatile unsigned char           TMR0                @ 0x001;\n#ifndef _LIB_BUILD\nasm(\"TMR0 equ 01h\");\n#endif\n\n\/\/ Register: PCL\nextern volatile unsigned char           PCL                 @ 0x002;\n#ifndef _LIB_BUILD\nasm(\"PCL equ 02h\");\n#endif\n\n\/\/ Register: STATUS\nextern volatile unsigned char           STATUS              @ 0x003;\n#ifndef _LIB_BUILD\nasm(\"STATUS equ 03h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned C                      :1;\n        unsigned DC                     :1;\n        unsigned Z                      :1;\n        unsigned nPD                    :1;\n        unsigned nTO                    :1;\n        unsigned RP                     :2;\n        unsigned IRP                    :1;\n    };\n    struct {\n        unsigned                        :5;\n        unsigned RP0                    :1;\n        unsigned RP1                    :1;\n    };\n    struct {\n        unsigned CARRY                  :1;\n    };\n    struct {\n        unsigned                        :2;\n        unsigned ZERO                   :1;\n    };\n} STATUSbits_t;\nextern volatile STATUSbits_t STATUSbits @ 0x003;\n\/\/ bitfield macros\n#define _STATUS_C_POSN                                      0x0\n#define _STATUS_C_POSITION                                  0x0\n#define _STATUS_C_SIZE                                      0x1\n#define _STATUS_C_LENGTH                                    0x1\n#define _STATUS_C_MASK                                      0x1\n#define _STATUS_DC_POSN                                     0x1\n#define _STATUS_DC_POSITION                                 0x1\n#define _STATUS_DC_SIZE                                     0x1\n#define _STATUS_DC_LENGTH                                   0x1\n#define _STATUS_DC_MASK                                     0x2\n#define _STATUS_Z_POSN                                      0x2\n#define _STATUS_Z_POSITION                                  0x2\n#define _STATUS_Z_SIZE                                      0x1\n#define _STATUS_Z_LENGTH                                    0x1\n#define _STATUS_Z_MASK                                      0x4\n#define _STATUS_nPD_POSN                                    0x3\n#define _STATUS_nPD_POSITION                                0x3\n#define _STATUS_nPD_SIZE                                    0x1\n#define _STATUS_nPD_LENGTH                                  0x1\n#define _STATUS_nPD_MASK                                    0x8\n#define _STATUS_nTO_POSN                                    0x4\n#define _STATUS_nTO_POSITION                                0x4\n#define _STATUS_nTO_SIZE                                    0x1\n#define _STATUS_nTO_LENGTH                                  0x1\n#define _STATUS_nTO_MASK                                    0x10\n#define _STATUS_RP_POSN                                     0x5\n#define _STATUS_RP_POSITION                                 0x5\n#define _STATUS_RP_SIZE                                     0x2\n#define _STATUS_RP_LENGTH                                   0x2\n#define _STATUS_RP_MASK                                     0x60\n#define _STATUS_IRP_POSN                                    0x7\n#define _STATUS_IRP_POSITION                                0x7\n#define _STATUS_IRP_SIZE                                    0x1\n#define _STATUS_IRP_LENGTH                                  0x1\n#define _STATUS_IRP_MASK                                    0x80\n#define _STATUS_RP0_POSN                                    0x5\n#define _STATUS_RP0_POSITION                                0x5\n#define _STATUS_RP0_SIZE                                    0x1\n#define _STATUS_RP0_LENGTH                                  0x1\n#define _STATUS_RP0_MASK                                    0x20\n#define _STATUS_RP1_POSN                                    0x6\n#define _STATUS_RP1_POSITION                                0x6\n#define _STATUS_RP1_SIZE                                    0x1\n#define _STATUS_RP1_LENGTH                                  0x1\n#define _STATUS_RP1_MASK                                    0x40\n#define _STATUS_CARRY_POSN                                  0x0\n#define _STATUS_CARRY_POSITION                              0x0\n#define _STATUS_CARRY_SIZE                                  0x1\n#define _STATUS_CARRY_LENGTH                                0x1\n#define _STATUS_CARRY_MASK                                  0x1\n#define _STATUS_ZERO_POSN                                   0x2\n#define _STATUS_ZERO_POSITION                               0x2\n#define _STATUS_ZERO_SIZE                                   0x1\n#define _STATUS_ZERO_LENGTH                                 0x1\n#define _STATUS_ZERO_MASK                                   0x4\n\n\/\/ Register: FSR\nextern volatile unsigned char           FSR                 @ 0x004;\n#ifndef _LIB_BUILD\nasm(\"FSR equ 04h\");\n#endif\n\n\/\/ Register: PORTA\nextern volatile unsigned char           PORTA               @ 0x005;\n#ifndef _LIB_BUILD\nasm(\"PORTA equ 05h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned RA0                    :1;\n        unsigned RA1                    :1;\n        unsigned RA2                    :1;\n        unsigned RA3                    :1;\n        unsigned RA4                    :1;\n    };\n} PORTAbits_t;\nextern volatile PORTAbits_t PORTAbits @ 0x005;\n\/\/ bitfield macros\n#define _PORTA_RA0_POSN                                     0x0\n#define _PORTA_RA0_POSITION                                 0x0\n#define _PORTA_RA0_SIZE                                     0x1\n#define _PORTA_RA0_LENGTH                                   0x1\n#define _PORTA_RA0_MASK                                     0x1\n#define _PORTA_RA1_POSN                                     0x1\n#define _PORTA_RA1_POSITION                                 0x1\n#define _PORTA_RA1_SIZE                                     0x1\n#define _PORTA_RA1_LENGTH                                   0x1\n#define _PORTA_RA1_MASK                                     0x2\n#define _PORTA_RA2_POSN                                     0x2\n#define _PORTA_RA2_POSITION                                 0x2\n#define _PORTA_RA2_SIZE                                     0x1\n#define _PORTA_RA2_LENGTH                                   0x1\n#define _PORTA_RA2_MASK                                     0x4\n#define _PORTA_RA3_POSN                                     0x3\n#define _PORTA_RA3_POSITION                                 0x3\n#define _PORTA_RA3_SIZE                                     0x1\n#define _PORTA_RA3_LENGTH                                   0x1\n#define _PORTA_RA3_MASK                                     0x8\n#define _PORTA_RA4_POSN                                     0x4\n#define _PORTA_RA4_POSITION                                 0x4\n#define _PORTA_RA4_SIZE                                     0x1\n#define _PORTA_RA4_LENGTH                                   0x1\n#define _PORTA_RA4_MASK                                     0x10\n\n\/\/ Register: PORTB\nextern volatile unsigned char           PORTB               @ 0x006;\n#ifndef _LIB_BUILD\nasm(\"PORTB equ 06h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned RB0                    :1;\n        unsigned RB1                    :1;\n        unsigned RB2                    :1;\n        unsigned RB3                    :1;\n        unsigned RB4                    :1;\n        unsigned RB5                    :1;\n        unsigned RB6                    :1;\n        unsigned RB7                    :1;\n    };\n} PORTBbits_t;\nextern volatile PORTBbits_t PORTBbits @ 0x006;\n\/\/ bitfield macros\n#define _PORTB_RB0_POSN                                     0x0\n#define _PORTB_RB0_POSITION                                 0x0\n#define _PORTB_RB0_SIZE                                     0x1\n#define _PORTB_RB0_LENGTH                                   0x1\n#define _PORTB_RB0_MASK                                     0x1\n#define _PORTB_RB1_POSN                                     0x1\n#define _PORTB_RB1_POSITION                                 0x1\n#define _PORTB_RB1_SIZE                                     0x1\n#define _PORTB_RB1_LENGTH                                   0x1\n#define _PORTB_RB1_MASK                                     0x2\n#define _PORTB_RB2_POSN                                     0x2\n#define _PORTB_RB2_POSITION                                 0x2\n#define _PORTB_RB2_SIZE                                     0x1\n#define _PORTB_RB2_LENGTH                                   0x1\n#define _PORTB_RB2_MASK                                     0x4\n#define _PORTB_RB3_POSN                                     0x3\n#define _PORTB_RB3_POSITION                                 0x3\n#define _PORTB_RB3_SIZE                                     0x1\n#define _PORTB_RB3_LENGTH                                   0x1\n#define _PORTB_RB3_MASK                                     0x8\n#define _PORTB_RB4_POSN                                     0x4\n#define _PORTB_RB4_POSITION                                 0x4\n#define _PORTB_RB4_SIZE                                     0x1\n#define _PORTB_RB4_LENGTH                                   0x1\n#define _PORTB_RB4_MASK                                     0x10\n#define _PORTB_RB5_POSN                                     0x5\n#define _PORTB_RB5_POSITION                                 0x5\n#define _PORTB_RB5_SIZE                                     0x1\n#define _PORTB_RB5_LENGTH                                   0x1\n#define _PORTB_RB5_MASK                                     0x20\n#define _PORTB_RB6_POSN                                     0x6\n#define _PORTB_RB6_POSITION                                 0x6\n#define _PORTB_RB6_SIZE                                     0x1\n#define _PORTB_RB6_LENGTH                                   0x1\n#define _PORTB_RB6_MASK                                     0x40\n#define _PORTB_RB7_POSN                                     0x7\n#define _PORTB_RB7_POSITION                                 0x7\n#define _PORTB_RB7_SIZE                                     0x1\n#define _PORTB_RB7_LENGTH                                   0x1\n#define _PORTB_RB7_MASK                                     0x80\n\n\/\/ Register: EEDATA\nextern volatile unsigned char           EEDATA              @ 0x008;\n#ifndef _LIB_BUILD\nasm(\"EEDATA equ 08h\");\n#endif\n\n\/\/ Register: EEADR\nextern volatile unsigned char           EEADR               @ 0x009;\n#ifndef _LIB_BUILD\nasm(\"EEADR equ 09h\");\n#endif\n\n\/\/ Register: PCLATH\nextern volatile unsigned char           PCLATH              @ 0x00A;\n#ifndef _LIB_BUILD\nasm(\"PCLATH equ 0Ah\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned PCLATH                 :5;\n    };\n} PCLATHbits_t;\nextern volatile PCLATHbits_t PCLATHbits @ 0x00A;\n\/\/ bitfield macros\n#define _PCLATH_PCLATH_POSN                                 0x0\n#define _PCLATH_PCLATH_POSITION                             0x0\n#define _PCLATH_PCLATH_SIZE                                 0x5\n#define _PCLATH_PCLATH_LENGTH                               0x5\n#define _PCLATH_PCLATH_MASK                                 0x1F\n\n\/\/ Register: INTCON\nextern volatile unsigned char           INTCON              @ 0x00B;\n#ifndef _LIB_BUILD\nasm(\"INTCON equ 0Bh\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned RBIF                   :1;\n        unsigned INTF                   :1;\n        unsigned T0IF                   :1;\n        unsigned RBIE                   :1;\n        unsigned INTE                   :1;\n        unsigned T0IE                   :1;\n        unsigned EEIE                   :1;\n        unsigned GIE                    :1;\n    };\n    struct {\n        unsigned                        :2;\n        unsigned TMR0IF                 :1;\n        unsigned                        :2;\n        unsigned TMR0IE                 :1;\n    };\n} INTCONbits_t;\nextern volatile INTCONbits_t INTCONbits @ 0x00B;\n\/\/ bitfield macros\n#define _INTCON_RBIF_POSN                                   0x0\n#define _INTCON_RBIF_POSITION                               0x0\n#define _INTCON_RBIF_SIZE                                   0x1\n#define _INTCON_RBIF_LENGTH                                 0x1\n#define _INTCON_RBIF_MASK                                   0x1\n#define _INTCON_INTF_POSN                                   0x1\n#define _INTCON_INTF_POSITION                               0x1\n#define _INTCON_INTF_SIZE                                   0x1\n#define _INTCON_INTF_LENGTH                                 0x1\n#define _INTCON_INTF_MASK                                   0x2\n#define _INTCON_T0IF_POSN                                   0x2\n#define _INTCON_T0IF_POSITION                               0x2\n#define _INTCON_T0IF_SIZE                                   0x1\n#define _INTCON_T0IF_LENGTH                                 0x1\n#define _INTCON_T0IF_MASK                                   0x4\n#define _INTCON_RBIE_POSN                                   0x3\n#define _INTCON_RBIE_POSITION                               0x3\n#define _INTCON_RBIE_SIZE                                   0x1\n#define _INTCON_RBIE_LENGTH                                 0x1\n#define _INTCON_RBIE_MASK                                   0x8\n#define _INTCON_INTE_POSN                                   0x4\n#define _INTCON_INTE_POSITION                               0x4\n#define _INTCON_INTE_SIZE                                   0x1\n#define _INTCON_INTE_LENGTH                                 0x1\n#define _INTCON_INTE_MASK                                   0x10\n#define _INTCON_T0IE_POSN                                   0x5\n#define _INTCON_T0IE_POSITION                               0x5\n#define _INTCON_T0IE_SIZE                                   0x1\n#define _INTCON_T0IE_LENGTH                                 0x1\n#define _INTCON_T0IE_MASK                                   0x20\n#define _INTCON_EEIE_POSN                                   0x6\n#define _INTCON_EEIE_POSITION                               0x6\n#define _INTCON_EEIE_SIZE                                   0x1\n#define _INTCON_EEIE_LENGTH                                 0x1\n#define _INTCON_EEIE_MASK                                   0x40\n#define _INTCON_GIE_POSN                                    0x7\n#define _INTCON_GIE_POSITION                                0x7\n#define _INTCON_GIE_SIZE                                    0x1\n#define _INTCON_GIE_LENGTH                                  0x1\n#define _INTCON_GIE_MASK                                    0x80\n#define _INTCON_TMR0IF_POSN                                 0x2\n#define _INTCON_TMR0IF_POSITION                             0x2\n#define _INTCON_TMR0IF_SIZE                                 0x1\n#define _INTCON_TMR0IF_LENGTH                               0x1\n#define _INTCON_TMR0IF_MASK                                 0x4\n#define _INTCON_TMR0IE_POSN                                 0x5\n#define _INTCON_TMR0IE_POSITION                             0x5\n#define _INTCON_TMR0IE_SIZE                                 0x1\n#define _INTCON_TMR0IE_LENGTH                               0x1\n#define _INTCON_TMR0IE_MASK                                 0x20\n\n\/\/ Register: OPTION_REG\nextern volatile unsigned char           OPTION_REG          @ 0x081;\n#ifndef _LIB_BUILD\nasm(\"OPTION_REG equ 081h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned PS                     :3;\n        unsigned PSA                    :1;\n        unsigned T0SE                   :1;\n        unsigned T0CS                   :1;\n        unsigned INTEDG                 :1;\n        unsigned nRBPU                  :1;\n    };\n    struct {\n        unsigned PS0                    :1;\n        unsigned PS1                    :1;\n        unsigned PS2                    :1;\n    };\n} OPTION_REGbits_t;\nextern volatile OPTION_REGbits_t OPTION_REGbits @ 0x081;\n\/\/ bitfield macros\n#define _OPTION_REG_PS_POSN                                 0x0\n#define _OPTION_REG_PS_POSITION                             0x0\n#define _OPTION_REG_PS_SIZE                                 0x3\n#define _OPTION_REG_PS_LENGTH                               0x3\n#define _OPTION_REG_PS_MASK                                 0x7\n#define _OPTION_REG_PSA_POSN                                0x3\n#define _OPTION_REG_PSA_POSITION                            0x3\n#define _OPTION_REG_PSA_SIZE                                0x1\n#define _OPTION_REG_PSA_LENGTH                              0x1\n#define _OPTION_REG_PSA_MASK                                0x8\n#define _OPTION_REG_T0SE_POSN                               0x4\n#define _OPTION_REG_T0SE_POSITION                           0x4\n#define _OPTION_REG_T0SE_SIZE                               0x1\n#define _OPTION_REG_T0SE_LENGTH                             0x1\n#define _OPTION_REG_T0SE_MASK                               0x10\n#define _OPTION_REG_T0CS_POSN                               0x5\n#define _OPTION_REG_T0CS_POSITION                           0x5\n#define _OPTION_REG_T0CS_SIZE                               0x1\n#define _OPTION_REG_T0CS_LENGTH                             0x1\n#define _OPTION_REG_T0CS_MASK                               0x20\n#define _OPTION_REG_INTEDG_POSN                             0x6\n#define _OPTION_REG_INTEDG_POSITION                         0x6\n#define _OPTION_REG_INTEDG_SIZE                             0x1\n#define _OPTION_REG_INTEDG_LENGTH                           0x1\n#define _OPTION_REG_INTEDG_MASK                             0x40\n#define _OPTION_REG_nRBPU_POSN                              0x7\n#define _OPTION_REG_nRBPU_POSITION                          0x7\n#define _OPTION_REG_nRBPU_SIZE                              0x1\n#define _OPTION_REG_nRBPU_LENGTH                            0x1\n#define _OPTION_REG_nRBPU_MASK                              0x80\n#define _OPTION_REG_PS0_POSN                                0x0\n#define _OPTION_REG_PS0_POSITION                            0x0\n#define _OPTION_REG_PS0_SIZE                                0x1\n#define _OPTION_REG_PS0_LENGTH                              0x1\n#define _OPTION_REG_PS0_MASK                                0x1\n#define _OPTION_REG_PS1_POSN                                0x1\n#define _OPTION_REG_PS1_POSITION                            0x1\n#define _OPTION_REG_PS1_SIZE                                0x1\n#define _OPTION_REG_PS1_LENGTH                              0x1\n#define _OPTION_REG_PS1_MASK                                0x2\n#define _OPTION_REG_PS2_POSN                                0x2\n#define _OPTION_REG_PS2_POSITION                            0x2\n#define _OPTION_REG_PS2_SIZE                                0x1\n#define _OPTION_REG_PS2_LENGTH                              0x1\n#define _OPTION_REG_PS2_MASK                                0x4\n\n\/\/ Register: TRISA\nextern volatile unsigned char           TRISA               @ 0x085;\n#ifndef _LIB_BUILD\nasm(\"TRISA equ 085h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned TRISA0                 :1;\n        unsigned TRISA1                 :1;\n        unsigned TRISA2                 :1;\n        unsigned TRISA3                 :1;\n        unsigned TRISA4                 :1;\n    };\n} TRISAbits_t;\nextern volatile TRISAbits_t TRISAbits @ 0x085;\n\/\/ bitfield macros\n#define _TRISA_TRISA0_POSN                                  0x0\n#define _TRISA_TRISA0_POSITION                              0x0\n#define _TRISA_TRISA0_SIZE                                  0x1\n#define _TRISA_TRISA0_LENGTH                                0x1\n#define _TRISA_TRISA0_MASK                                  0x1\n#define _TRISA_TRISA1_POSN                                  0x1\n#define _TRISA_TRISA1_POSITION                              0x1\n#define _TRISA_TRISA1_SIZE                                  0x1\n#define _TRISA_TRISA1_LENGTH                                0x1\n#define _TRISA_TRISA1_MASK                                  0x2\n#define _TRISA_TRISA2_POSN                                  0x2\n#define _TRISA_TRISA2_POSITION                              0x2\n#define _TRISA_TRISA2_SIZE                                  0x1\n#define _TRISA_TRISA2_LENGTH                                0x1\n#define _TRISA_TRISA2_MASK                                  0x4\n#define _TRISA_TRISA3_POSN                                  0x3\n#define _TRISA_TRISA3_POSITION                              0x3\n#define _TRISA_TRISA3_SIZE                                  0x1\n#define _TRISA_TRISA3_LENGTH                                0x1\n#define _TRISA_TRISA3_MASK                                  0x8\n#define _TRISA_TRISA4_POSN                                  0x4\n#define _TRISA_TRISA4_POSITION                              0x4\n#define _TRISA_TRISA4_SIZE                                  0x1\n#define _TRISA_TRISA4_LENGTH                                0x1\n#define _TRISA_TRISA4_MASK                                  0x10\n\n\/\/ Register: TRISB\nextern volatile unsigned char           TRISB               @ 0x086;\n#ifndef _LIB_BUILD\nasm(\"TRISB equ 086h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned TRISB0                 :1;\n        unsigned TRISB1                 :1;\n        unsigned TRISB2                 :1;\n        unsigned TRISB3                 :1;\n        unsigned TRISB4                 :1;\n        unsigned TRISB5                 :1;\n        unsigned TRISB6                 :1;\n        unsigned TRISB7                 :1;\n    };\n} TRISBbits_t;\nextern volatile TRISBbits_t TRISBbits @ 0x086;\n\/\/ bitfield macros\n#define _TRISB_TRISB0_POSN                                  0x0\n#define _TRISB_TRISB0_POSITION                              0x0\n#define _TRISB_TRISB0_SIZE                                  0x1\n#define _TRISB_TRISB0_LENGTH                                0x1\n#define _TRISB_TRISB0_MASK                                  0x1\n#define _TRISB_TRISB1_POSN                                  0x1\n#define _TRISB_TRISB1_POSITION                              0x1\n#define _TRISB_TRISB1_SIZE                                  0x1\n#define _TRISB_TRISB1_LENGTH                                0x1\n#define _TRISB_TRISB1_MASK                                  0x2\n#define _TRISB_TRISB2_POSN                                  0x2\n#define _TRISB_TRISB2_POSITION                              0x2\n#define _TRISB_TRISB2_SIZE                                  0x1\n#define _TRISB_TRISB2_LENGTH                                0x1\n#define _TRISB_TRISB2_MASK                                  0x4\n#define _TRISB_TRISB3_POSN                                  0x3\n#define _TRISB_TRISB3_POSITION                              0x3\n#define _TRISB_TRISB3_SIZE                                  0x1\n#define _TRISB_TRISB3_LENGTH                                0x1\n#define _TRISB_TRISB3_MASK                                  0x8\n#define _TRISB_TRISB4_POSN                                  0x4\n#define _TRISB_TRISB4_POSITION                              0x4\n#define _TRISB_TRISB4_SIZE                                  0x1\n#define _TRISB_TRISB4_LENGTH                                0x1\n#define _TRISB_TRISB4_MASK                                  0x10\n#define _TRISB_TRISB5_POSN                                  0x5\n#define _TRISB_TRISB5_POSITION                              0x5\n#define _TRISB_TRISB5_SIZE                                  0x1\n#define _TRISB_TRISB5_LENGTH                                0x1\n#define _TRISB_TRISB5_MASK                                  0x20\n#define _TRISB_TRISB6_POSN                                  0x6\n#define _TRISB_TRISB6_POSITION                              0x6\n#define _TRISB_TRISB6_SIZE                                  0x1\n#define _TRISB_TRISB6_LENGTH                                0x1\n#define _TRISB_TRISB6_MASK                                  0x40\n#define _TRISB_TRISB7_POSN                                  0x7\n#define _TRISB_TRISB7_POSITION                              0x7\n#define _TRISB_TRISB7_SIZE                                  0x1\n#define _TRISB_TRISB7_LENGTH                                0x1\n#define _TRISB_TRISB7_MASK                                  0x80\n\n\/\/ Register: EECON1\nextern volatile unsigned char           EECON1              @ 0x088;\n#ifndef _LIB_BUILD\nasm(\"EECON1 equ 088h\");\n#endif\n\/\/ bitfield definitions\ntypedef union {\n    struct {\n        unsigned RD                     :1;\n        unsigned WR                     :1;\n        unsigned WREN                   :1;\n        unsigned WRERR                  :1;\n        unsigned EEIF                   :1;\n    };\n} EECON1bits_t;\nextern volatile EECON1bits_t EECON1bits @ 0x088;\n\/\/ bitfield macros\n#define _EECON1_RD_POSN                                     0x0\n#define _EECON1_RD_POSITION                                 0x0\n#define _EECON1_RD_SIZE                                     0x1\n#define _EECON1_RD_LENGTH                                   0x1\n#define _EECON1_RD_MASK                                     0x1\n#define _EECON1_WR_POSN                                     0x1\n#define _EECON1_WR_POSITION                                 0x1\n#define _EECON1_WR_SIZE                                     0x1\n#define _EECON1_WR_LENGTH                                   0x1\n#define _EECON1_WR_MASK                                     0x2\n#define _EECON1_WREN_POSN                                   0x2\n#define _EECON1_WREN_POSITION                               0x2\n#define _EECON1_WREN_SIZE                                   0x1\n#define _EECON1_WREN_LENGTH                                 0x1\n#define _EECON1_WREN_MASK                                   0x4\n#define _EECON1_WRERR_POSN                                  0x3\n#define _EECON1_WRERR_POSITION                              0x3\n#define _EECON1_WRERR_SIZE                                  0x1\n#define _EECON1_WRERR_LENGTH                                0x1\n#define _EECON1_WRERR_MASK                                  0x8\n#define _EECON1_EEIF_POSN                                   0x4\n#define _EECON1_EEIF_POSITION                               0x4\n#define _EECON1_EEIF_SIZE                                   0x1\n#define _EECON1_EEIF_LENGTH                                 0x1\n#define _EECON1_EEIF_MASK                                   0x10\n\n\/\/ Register: EECON2\nextern volatile unsigned char           EECON2              @ 0x089;\n#ifndef _LIB_BUILD\nasm(\"EECON2 equ 089h\");\n#endif\n\n\/*\n * Bit Definitions\n *  *\/\n#define _DEPRECATED __attribute__((__deprecated__))\n#ifndef BANKMASK\n#define BANKMASK(addr) ((addr)&07Fh)\n#endif\nextern volatile __bit                   CARRY               @ (((unsigned) &STATUS)*8) + 0;\n#define                                 CARRY_bit           BANKMASK(STATUS), 0\nextern volatile __bit                   DC                  @ (((unsigned) &STATUS)*8) + 1;\n#define                                 DC_bit              BANKMASK(STATUS), 1\nextern volatile __bit                   EEIE                @ (((unsigned) &INTCON)*8) + 6;\n#define                                 EEIE_bit            BANKMASK(INTCON), 6\nextern volatile __bit                   EEIF                @ (((unsigned) &EECON1)*8) + 4;\n#define                                 EEIF_bit            BANKMASK(EECON1), 4\nextern volatile __bit                   GIE                 @ (((unsigned) &INTCON)*8) + 7;\n#define                                 GIE_bit             BANKMASK(INTCON), 7\nextern volatile __bit                   INTE                @ (((unsigned) &INTCON)*8) + 4;\n#define                                 INTE_bit            BANKMASK(INTCON), 4\nextern volatile __bit                   INTEDG              @ (((unsigned) &OPTION_REG)*8) + 6;\n#define                                 INTEDG_bit          BANKMASK(OPTION_REG), 6\nextern volatile __bit                   INTF                @ (((unsigned) &INTCON)*8) + 1;\n#define                                 INTF_bit            BANKMASK(INTCON), 1\nextern volatile __bit                   IRP                 @ (((unsigned) &STATUS)*8) + 7;\n#define                                 IRP_bit             BANKMASK(STATUS), 7\nextern volatile __bit                   PS0                 @ (((unsigned) &OPTION_REG)*8) + 0;\n#define                                 PS0_bit             BANKMASK(OPTION_REG), 0\nextern volatile __bit                   PS1                 @ (((unsigned) &OPTION_REG)*8) + 1;\n#define                                 PS1_bit             BANKMASK(OPTION_REG), 1\nextern volatile __bit                   PS2                 @ (((unsigned) &OPTION_REG)*8) + 2;\n#define                                 PS2_bit             BANKMASK(OPTION_REG), 2\nextern volatile __bit                   PSA                 @ (((unsigned) &OPTION_REG)*8) + 3;\n#define                                 PSA_bit             BANKMASK(OPTION_REG), 3\nextern volatile __bit                   RA0                 @ (((unsigned) &PORTA)*8) + 0;\n#define                                 RA0_bit             BANKMASK(PORTA), 0\nextern volatile __bit                   RA1                 @ (((unsigned) &PORTA)*8) + 1;\n#define                                 RA1_bit             BANKMASK(PORTA), 1\nextern volatile __bit                   RA2                 @ (((unsigned) &PORTA)*8) + 2;\n#define                                 RA2_bit             BANKMASK(PORTA), 2\nextern volatile __bit                   RA3                 @ (((unsigned) &PORTA)*8) + 3;\n#define                                 RA3_bit             BANKMASK(PORTA), 3\nextern volatile __bit                   RA4                 @ (((unsigned) &PORTA)*8) + 4;\n#define                                 RA4_bit             BANKMASK(PORTA), 4\nextern volatile __bit                   RB0                 @ (((unsigned) &PORTB)*8) + 0;\n#define                                 RB0_bit             BANKMASK(PORTB), 0\nextern volatile __bit                   RB1                 @ (((unsigned) &PORTB)*8) + 1;\n#define                                 RB1_bit             BANKMASK(PORTB), 1\nextern volatile __bit                   RB2                 @ (((unsigned) &PORTB)*8) + 2;\n#define                                 RB2_bit             BANKMASK(PORTB), 2\nextern volatile __bit                   RB3                 @ (((unsigned) &PORTB)*8) + 3;\n#define                                 RB3_bit             BANKMASK(PORTB), 3\nextern volatile __bit                   RB4                 @ (((unsigned) &PORTB)*8) + 4;\n#define                                 RB4_bit             BANKMASK(PORTB), 4\nextern volatile __bit                   RB5                 @ (((unsigned) &PORTB)*8) + 5;\n#define                                 RB5_bit             BANKMASK(PORTB), 5\nextern volatile __bit                   RB6                 @ (((unsigned) &PORTB)*8) + 6;\n#define                                 RB6_bit             BANKMASK(PORTB), 6\nextern volatile __bit                   RB7                 @ (((unsigned) &PORTB)*8) + 7;\n#define                                 RB7_bit             BANKMASK(PORTB), 7\nextern volatile __bit                   RBIE                @ (((unsigned) &INTCON)*8) + 3;\n#define                                 RBIE_bit            BANKMASK(INTCON), 3\nextern volatile __bit                   RBIF                @ (((unsigned) &INTCON)*8) + 0;\n#define                                 RBIF_bit            BANKMASK(INTCON), 0\nextern volatile __bit                   RD                  @ (((unsigned) &EECON1)*8) + 0;\n#define                                 RD_bit              BANKMASK(EECON1), 0\nextern volatile __bit                   RP0                 @ (((unsigned) &STATUS)*8) + 5;\n#define                                 RP0_bit             BANKMASK(STATUS), 5\nextern volatile __bit                   RP1                 @ (((unsigned) &STATUS)*8) + 6;\n#define                                 RP1_bit             BANKMASK(STATUS), 6\nextern volatile __bit                   T0CS                @ (((unsigned) &OPTION_REG)*8) + 5;\n#define                                 T0CS_bit            BANKMASK(OPTION_REG), 5\nextern volatile __bit                   T0IE                @ (((unsigned) &INTCON)*8) + 5;\n#define                                 T0IE_bit            BANKMASK(INTCON), 5\nextern volatile __bit                   T0IF                @ (((unsigned) &INTCON)*8) + 2;\n#define                                 T0IF_bit            BANKMASK(INTCON), 2\nextern volatile __bit                   T0SE                @ (((unsigned) &OPTION_REG)*8) + 4;\n#define                                 T0SE_bit            BANKMASK(OPTION_REG), 4\nextern volatile __bit                   TMR0IE              @ (((unsigned) &INTCON)*8) + 5;\n#define                                 TMR0IE_bit          BANKMASK(INTCON), 5\nextern volatile __bit                   TMR0IF              @ (((unsigned) &INTCON)*8) + 2;\n#define                                 TMR0IF_bit          BANKMASK(INTCON), 2\nextern volatile __bit                   TRISA0              @ (((unsigned) &TRISA)*8) + 0;\n#define                                 TRISA0_bit          BANKMASK(TRISA), 0\nextern volatile __bit                   TRISA1              @ (((unsigned) &TRISA)*8) + 1;\n#define                                 TRISA1_bit          BANKMASK(TRISA), 1\nextern volatile __bit                   TRISA2              @ (((unsigned) &TRISA)*8) + 2;\n#define                                 TRISA2_bit          BANKMASK(TRISA), 2\nextern volatile __bit                   TRISA3              @ (((unsigned) &TRISA)*8) + 3;\n#define                                 TRISA3_bit          BANKMASK(TRISA), 3\nextern volatile __bit                   TRISA4              @ (((unsigned) &TRISA)*8) + 4;\n#define                                 TRISA4_bit          BANKMASK(TRISA), 4\nextern volatile __bit                   TRISB0              @ (((unsigned) &TRISB)*8) + 0;\n#define                                 TRISB0_bit          BANKMASK(TRISB), 0\nextern volatile __bit                   TRISB1              @ (((unsigned) &TRISB)*8) + 1;\n#define                                 TRISB1_bit          BANKMASK(TRISB), 1\nextern volatile __bit                   TRISB2              @ (((unsigned) &TRISB)*8) + 2;\n#define                                 TRISB2_bit          BANKMASK(TRISB), 2\nextern volatile __bit                   TRISB3              @ (((unsigned) &TRISB)*8) + 3;\n#define                                 TRISB3_bit          BANKMASK(TRISB), 3\nextern volatile __bit                   TRISB4              @ (((unsigned) &TRISB)*8) + 4;\n#define                                 TRISB4_bit          BANKMASK(TRISB), 4\nextern volatile __bit                   TRISB5              @ (((unsigned) &TRISB)*8) + 5;\n#define                                 TRISB5_bit          BANKMASK(TRISB), 5\nextern volatile __bit                   TRISB6              @ (((unsigned) &TRISB)*8) + 6;\n#define                                 TRISB6_bit          BANKMASK(TRISB), 6\nextern volatile __bit                   TRISB7              @ (((unsigned) &TRISB)*8) + 7;\n#define                                 TRISB7_bit          BANKMASK(TRISB), 7\nextern volatile __bit                   WR                  @ (((unsigned) &EECON1)*8) + 1;\n#define                                 WR_bit              BANKMASK(EECON1), 1\nextern volatile __bit                   WREN                @ (((unsigned) &EECON1)*8) + 2;\n#define                                 WREN_bit            BANKMASK(EECON1), 2\nextern volatile __bit                   WRERR               @ (((unsigned) &EECON1)*8) + 3;\n#define                                 WRERR_bit           BANKMASK(EECON1), 3\nextern volatile __bit                   ZERO                @ (((unsigned) &STATUS)*8) + 2;\n#define                                 ZERO_bit            BANKMASK(STATUS), 2\nextern volatile __bit                   nPD                 @ (((unsigned) &STATUS)*8) + 3;\n#define                                 nPD_bit             BANKMASK(STATUS), 3\nextern volatile __bit                   nRBPU               @ (((unsigned) &OPTION_REG)*8) + 7;\n#define                                 nRBPU_bit           BANKMASK(OPTION_REG), 7\nextern volatile __bit                   nTO                 @ (((unsigned) &STATUS)*8) + 4;\n#define                                 nTO_bit             BANKMASK(STATUS), 4\n\n#endif \/\/ _PIC16F84A_H_\n<\/pre>\n\nBurada, t\u00fcm register tan\u0131mlar\u0131n\u0131n nas\u0131l yap\u0131ld\u0131\u011f\u0131na dikkat ediniz :) Bizim G\u00f6m\u00fcl\u00fc C yaz\u0131 dizisini tamamen okuyan herkes i\u00e7in burada ne yap\u0131ld\u0131\u011f\u0131n\u0131 anlamak kolay olacakt\u0131r. Yine de anlamad\u0131\u011f\u0131n\u0131z yerler olursa sorunuz :) \u015eimdi merhaba d\u00fcnya kodumuzdaki register'lar\u0131 \u00f6zellikle inceleyelim.\n\n
...\n\/\/ Register: PORTB\nextern volatile unsigned char           PORTB               @ 0x006;\n#ifndef _LIB_BUILD\nasm(\"PORTB equ 06h\");\n#endif\n\n...\n\/\/ Register: TRISB\nextern volatile unsigned char           TRISB               @ 0x086;\n#ifndef _LIB_BUILD\nasm(\"TRISB equ 086h\");\n#endif<\/pre>\n\nBurada demi\u015fler ki PORTB diye bir de\u011fi\u015fken yarat\u0131yoruz ve bu bellekteki 0x006 numaral\u0131 adrese kar\u015f\u0131l\u0131k d\u00fc\u015f\u00fcyor. Yine benzer \u015fekilde\u00a0TRISB diye bir de\u011fi\u015fken yarat\u0131yoruz ve bu bellekteki 0x086 numaral\u0131 adrese kar\u015f\u0131l\u0131k d\u00fc\u015f\u00fcyor. Bu bilgileri datasheet'teki <\/a>bellek haritas\u0131ndan aynen do\u011frulamak m\u00fcmk\u00fcn. Zaten oradan bak\u0131p yazm\u0131\u015flar :) Ama ay\u0131betmi\u015fler... \u00c7\u00fcnk\u00fc t\u00fcm register'lar i\u00e7in kafadan de\u011fi\u015fken tan\u0131mlanm\u0131\u015f. Bu, \u00f6demesi a\u011f\u0131r bir bedel. Ayr\u0131ca @ operat\u00f6r\u00fc standart bir operat\u00f6r de\u011fil. Dolay\u0131s\u0131yla bu tan\u0131mlar, platform ba\u011f\u0131ml\u0131l\u0131\u011f\u0131 yaratmakta ve kodlar\u0131n ta\u015f\u0131nabilirli\u011fini negatif etkilemekte. Bunlara bir ayar \u00e7ekmemiz ka\u00e7\u0131n\u0131lmaz duruyor :)\n\n\u015eimdi, bu noktaya geldikten sonra, gelene\u011fimizi uygulayal\u0131m ve yine header kullanmaks\u0131z\u0131n merhaba d\u00fcnya kodumuzu yeniden yazal\u0131m :)\n\n
#define myTRISB (*( volatile unsigned char*)0x086)\n#define myPORTB (*( volatile unsigned char*)0x006)\n\nvoid main() {\n    myTRISB = 0;\n    myPORTB = 1;\n    while(1);\n}\n<\/pre>\n\nG\u00f6rd\u00fc\u011f\u00fcn\u00fcz \u00fczere, kodda ne bir k\u00fct\u00fcphane kulland\u0131k, ne de bir de\u011fi\u015fken! Zaten kodumuzda, merhaba d\u00fcnya kodundaki gereksiz \u015feylerin hi\u00e7 birisi yok. Register\u00a0tan\u0131mlar\u0131n\u0131 da \u00e7ok \u00e7ok daha verimli \u015fekilde yapt\u0131\u011f\u0131m\u0131z\u0131 gururla huzurlar\u0131n\u0131za sunar\u0131m :) 0 byte de\u011fi\u015fken kullanarak, yine ledimizi yakt\u0131k!\n\n\"PIC16F84A_3\"<\/a>\n\nBuradan gerekli ibretleri l\u00fctfen alal\u0131m :) San\u0131yorum ki, \"Abi PIC programlama yaparken Hi-Tech compiler CSS'den iyiymi\u015f yaa\" filan gibi geyiklere art\u0131k bolca g\u00fclersiniz. Hi\u00e7birine ihtiyac\u0131m\u0131z yok, sadece tekerle\u011fi yeniden icad etmemek i\u00e7in onlar\u0131 ara\u00e7 olarak kullan\u0131yoruz ;)\n\nSonraki yaz\u0131mda bu temellerin \u00fczerine, giri\u015f \u00e7\u0131k\u0131\u015f i\u015flemleriyle ilgili detayl\u0131 bir yap\u0131 in\u015fa etmeyi planl\u0131yorum. Dilerim sizler i\u00e7in de faydal\u0131 ve e\u011flenceli bir yaz\u0131 olmu\u015ftur.\n\n\u015eimdi devam...\n\n[su_button url=\"http:\/\/ozenozkaya.com\/blog\/?p=378\" style=\"3d\"\u00a0icon=\"icon: arrow-circle-o-left\"]\u00d6nceki Sayfa[\/su_button] \u00a0[su_button url=\"http:\/\/ozenozkaya.com\/blog\/?p=414\" style=\"3d\" icon=\"icon: arrow-circle-right\"]Sonraki Sayfa[\/su_button]\n\n ","_tr_post_name":"pic-programlama-3-merhaba-dunya-analizi","_tr_post_excerpt":"","_tr_post_title":"PIC Programlama \u2013 3 - Merhaba D\u00fcnya Analizi","_en_post_content":"","_en_post_name":"","_en_post_excerpt":"","_en_post_title":"","edit_language":"tr","jetpack_post_was_ever_published":false,"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":true,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"enabled":false},"version":2}},"categories":[2,3],"tags":[],"class_list":["post-403","post","type-post","status-publish","format-standard","hentry","category-elektronik","category-gomulu-sistemler"],"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"jetpack_shortlink":"https:\/\/wp.me\/p5gWM6-6v","jetpack-related-posts":[],"_links":{"self":[{"href":"http:\/\/ozenozkaya.com\/blog\/index.php?rest_route=\/wp\/v2\/posts\/403","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/ozenozkaya.com\/blog\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/ozenozkaya.com\/blog\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/ozenozkaya.com\/blog\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/ozenozkaya.com\/blog\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=403"}],"version-history":[{"count":0,"href":"http:\/\/ozenozkaya.com\/blog\/index.php?rest_route=\/wp\/v2\/posts\/403\/revisions"}],"wp:attachment":[{"href":"http:\/\/ozenozkaya.com\/blog\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=403"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/ozenozkaya.com\/blog\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=403"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/ozenozkaya.com\/blog\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=403"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}